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Breaking Down UPLI: A Protocol-Level Perspective on UALink 200

• 3 minute read

In the evolving landscape of high-performance computing, particularly in AI and ML workloads, efficient interconnects between accelerators are critical. The Ultra Accelerator Link (UALink) 200 specification introduces a robust framework for scalable, low-latency communication across accelerators. UALink Protocol Level Interface (UPLI)—a pivotal component that defines how devices exchange data and control information. This blog explores the UPLI interface definition and operation rules, offering insights into its structure, functionality, and significance in multi-node accelerator systems.

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle.

UPLI supports:

  • Split requests and responses for bandwidth optimization.
  • Transaction identification tags for managing multiple outstanding requests.
  • Read, write, atomic, and vendor-defined operations, including UPLI write messages.

UPLI Channels and Their Roles

The UPLI interface is composed of four distinct channels, each serving a specific purpose:

  1. Request channel: Initiates transactions with details like address, command type, source/destination IDs, and transaction tags.
  2. Originator data channel: Carries data for write, atomic, and UPLI write message requests. It includes byte enables and beat indicators.
  3. Read response/data channel: Returns data for read and atomicR requests. It includes status, offset, beat count, and error indicators.
  4. Write response channel: Provides status feedback for write and atomicNR requests.

Each channel operates in Time Division Multiplexing (TDM) mode, allowing multiple ports to share the interface efficiently.

Transaction Lifecycle

A typical UPLI transaction follows this sequence:

  1. Request initiation: The originator sends a request on the request channel. If it's a data-carrying operation (e.g., Write), the first data beat is sent simultaneously on the originator data channel.
  2. Routing and processing: The request traverses through intermediate logic blocks (e.g., switches), which may reorder transactions based on system rules.
  3. Response Generation: The Completer processes the Request and sends back a Response on the appropriate channel—Read response/data or write response.
  4. Credit-based flow control: UPLI uses a credit system to manage flow control. Credits are returned from the receiver to the sender, ensuring buffer availability and preventing congestion.

Key Operational Rules

  • Atomicity: UPLI supports single-copy atomicity, ensuring that memory operations are performed without fragmentation.
  • Ordering: Requests are ordered per source-destination pair. In strict security modes, all requests are strictly ordered.
  • Error handling: UPLI includes mechanisms for detecting and handling control, data, and protocol errors. Errors trigger drop modes or isolation modes to maintain system integrity.
  • Reset and handshake: The interface includes a handshake protocol using ClkReq and ClkAck signals to establish connections post-reset.

UPLI Stack component

Core elements:

  • UPLI originator: Sends Req and OrigData channels.
  • UPLI completer: Receives Rd Rsp/Data and Wr Rsp channels.
  • Transport Layer (TL): Converts UPLI channels into TL Flits and vice versa.

Data flow:

  1. UPLI → TL: Originator/completer channels are packed into TL Flits.
  2. TL → DL: TL Flits are grouped, CRC and headers added to form DL Flits.
  3. DL → PL: DL Flits are FEC-encoded into codewords, serialized, and transmitted.
  4. Reverse path: Received codewords are decoded and unpacked back up the stack.

Communication model:

  • Bi-directional and symmetric:
    • Accelerator’s UPLI originator Left right arrow Switch’s UPLI completer
    • Switch’s UPLI originator Left right arrow Accelerator’s UPLI completer

 

The UPLI interface in UALink 200G is a cornerstone of next-generation accelerator interconnects. Its well-defined structure and operational rules provide a reliable foundation for building scalable, coherent, and high-performance multi-node systems. As AI continues to push the boundaries of compute infrastructure, interfaces like UPLI will play a vital role in enabling seamless, efficient communication across diverse accelerator ecosystems.