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The Link equalization procedure enables components to adjust the Transmitter and the Receiver setup of each Lane to improve the signal quality and meet the requirements, when operating at 8.0 GT/s and higher data rates. All the Lanes that are associated with the LTSSM (i.e., those Lanes that are currently operational or may be operational in the future due to Link Up-configure) must participate in the Equalization procedure.
Components must arrive at the appropriate Transmitter setup for all the operating conditions and data rates they will encounter.
The equalization procedure can be initiated either autonomously or by software. It is strongly recommended that components use the autonomous mechanism. However, a component that chooses not to participate in the autonomous mechanism must have its associated software to ensure that the software-based mechanism is applied.
How does the PCIe 6.0 Equalization procedure differ from the previous generations?
The major change is the usage of TS0 Ordered sets during phase 0 and phase 1 of the Equalization procedure.
PCIe 6.0 introduced a new type of Ordered set, TS0 which is analogous in functionality to that of TS1.TS0 has alternate bits set to 0, to enable its representation using only two voltage levels (0 and 3) in PAM4, which is essentially equivalent to NRZ.
This is done to ease the error detection in the initial equalization stages when the link is not fully trained.
All the TS0 to TS1 transitions are expected and initiated by a Port so that its receiver is prepared for the NRZ to PAM4 transition.
The important thing to note here is that TS0 needs to be sent in the beginning of the phase 2 for Downstream Port and at the beginning of the phase 3 for the Upstream Port, then followed by TS1.
Current Data rate/Port
TS0 followed TS1
Other Changes involve
What Does PCIe 6.0 Equalization Process Go Through?
The process of equalization in PCIe 6.0 remains the same as in previous generations, except for ordered sets exchanged in each phase (i.e., usage of TS0).
The transition to PCIe 6.0 can only be made from PCIe 5.0 speed. To move to 64.0 GT/s, the link should be up and running at 32.0 GT/s L0. There is no provision to skip or bypass Equalization.
Though in PCIe 5.0 there is a provision to skip equalization, termed Enhanced Link Behavior which was introduced in PCIe 5.0 specification.
The Equalization process starts as the Downstream Port first enters Phase 1 and sends TS0/TS1 Ordered Sets using the Transmitter preset settings for the current data rate of operation. After two consecutive TS0 ordered sets are received with Retimer Equalization Extend bit set to 0b, the EC field is set to 01b. In the TS0/TS1 Ordered Sets, the EC field is set to 01b. For TS0 ordered sets, the EC field is initially set to 00b. The Transmitter Preset bits of each Lane is set to the value of its corresponding Transmitter preset setting for the current data rate. The FS and LF fields are set to the appropriate values. The Pre-cursor coefficient, Cursor coefficient, and Post-cursor Coefficient fields are set to values corresponding to the Lane's Transmitter Preset bits if TS1 Ordered Sets are transmitted.
The upstream port enters phase 0 and sends TS0 Ordered Sets using the 64.0 GT/s Transmitter settings specified by the Transmitter Preset bits received in the 128b/130b EQ TS2 Ordered Sets at 32.0 GT/s during the most recent transition to the 64.0 GT/s data rate.
As I mentioned, the process goes the same, except TS0 will be used for requesting preset/coefficient change in 64.0 GT/s Equalization.
The rules for Reserved or unsupported Transmitter Presets/Coefficients remain were the same in previous generations. So, no change there.
The mechanism for re-do Equalization remains same as in previous Generations. If the Downstream Port detects equalization problems or the Upstream Port made makes an equalization redo request, the Downstream Port may redo equalization before proceeding to operate at the data rate where the equalization failed or performing equalization at a higher data rate.
Again, point to note- the attempt to redo equalization at 64 GT/s is only possible from data rate of 32 GT/s
Equalization to 64.0 GT/s from 2.5 GT/s or 5.0 GT/s is not supported. All equalization procedures at the 64.0 GT/s data rate, including re-equalization, must only be initiated from the 32.0 GT/s data rate.
Equalization at a data rate from a data rate equal to the target equalization data rate i.e 64.0 GT/s equalization from 64.0 GT/s is not supported.
With the latest addition of PCIe 6.0, Transmitter Equalization continues to make an important feature in verifying the reliability of the link.
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