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Scaling chip size and increasing functionality over SoCs has increased complexity and verification time. Verification teams are concerned about the bugs that may have slipped to silicon earlier and their discovery rate. Moreover, completing the verification and achieving the desired coverage is tricky. It looks arduous to complete the verification and meet the time constraints, especially when the specifications change often!
Early bug detection, productivity improvements without compromising verification efficiency, and regression throughput are the primary goals for verification teams. Design and verification engineers (DVE) need a tool, app, or technology that can help to accelerate coverage convergence, expose bugs early in the design cycle, and reduce the debugging effort. Cadence Xcelium simulator and the related apps, as in Fig. 1, enable design teams to achieve the highest verification performance, both IP and full chip levels of modern SoC design.
Figure 1: Xcelium Apps
Cadence Xcelium apps are the next step in the evolution of logic simulation and help DVEs meet their dynamic verification in time. This blog discusses how the Cadence Xcelium machine learning (ML) app quickly finds more bugs and corner cases, accelerates coverage closure, and saves resources by compressing the regressions up to 5X, thereby improving regression efficiency.
The Cadence Xcelium machine learning (ML) app leverages proprietary ML technology and learns iteratively over an entire simulation regression to achieve early coverage closure, as shown in Fig. 2.
Figure 2: Xcelium ML: Coverage with Iterative learning
It uses a training set of data from all ML clients to build up the models, thereby providing the correlation between randomization data and coverage data. These models are used to build new regressions targeted towards the goals as set by the user. It supports single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload, as shown in Fig 3.
Figure 3: Xcelium ML enables ~5X verication faster closure on randomized regressions
Cadence Xcellium ML app reduces the CPU hours and compresses the regression. It improves the throughput by compressing the regression, as illustrated in Fig. 4. It also helps target specific areas of the design to focus the run on explicit behaviors. In both cases, it increases the hit rate of target coverage. Further, it helps achieve similar coverage with condensed regressions in fewer simulation cycles or captures more bugs around specific coverage points.
Figure 4: Xcelium ML Benefits
This app provides a view of coverage prediction in the prediction graph depicting the number of runs required to achieve/ regain the targeted coverage with the generated regression. It also provides analytics to the user to get a better hold of machine learning (ML) models to get more insights into regression generation. Analytics like
It plays different roles during different stages of design, as mentioned below
Cadence Xcelium simulator with the ML app efficiently tests corner cases and helps customize the functional and code coverage. Using the Cadence Xcelium ML app improves the efficiency of the regression environment, saves CPU hours, improves bug-hunting efficiency, and accelerates coverage closure. Customers using the Cadence Xcelium ML app have experienced shorter turnaround times in the fully random regression run to reach 99% function coverage of the original.