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ErinGrant

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webinar
xcelium
verification

Streamlining Digital Front-End Design and Verification with Cadence Tools

29 Oct 2025 • 1 minute read

Plan, Simulate, and Debug: Streamlining Digital Front-End Design and Verification with Cadence Tools

Navigating the Cadence front-end design and verification tool suite can be seamless when approached as an integrated flow.  

Join the Cadence Training team for this two-part, extended webinar series where we do just that. Get insights from industry experts who guide you through a complete, integrated verification flow, from initial design to coverage closure. You’ll learn about interactive features, experience live tool demonstrations, and get answers from Cadence experts in our live Q&A sessions.

Agenda:

  • Introduction to SystemVerilog testbench development
  • Metric-Driven Verification (MDV) methodology focusing on the first phase of planning
  • UVM methodology concepts for building verification infrastructure
  • Fast, accurate simulation with Xcelium Logic Simulator
  • Debugging with Verisium Debug

Date and Time / Day #1

Thursday, November 13
06:00 – 08:00 PST San Jose/9:00 – 11:00 EST New York/14:00 – 16:00 GMT London/15:00 – 17:00 CET Berlin/16:00 – 18:00 IST Jerusalem/19:30 – 21:30 IST Bengaluru (Bangalore)/22:00 – 12:00) CST Beijing

REGISTER

To register for this webinar, sign in with your Cadence ASK* account (email ID and password), then select Enroll. You’ll receive a confirmation email with all login details.

A quick reminder:

  • If you haven’t received a registration confirmation within one hour of registering, please check your spam folder and ensure your pop-up blockers are off, and cookies are enabled.
  • For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com.
  • To view our complete training offerings, visit the Cadence Training website.

 Want to dive deep into the topics?

Enroll in our free online training courses.

SystemVerilog for Design and Verification

SystemVerilog Accelerated Verification with UVM

Xcelium Simulator

Verisium Debug

Verisium Manager

There is also a Digital Badge available for these trainings.            

*If you don’t have an ASK account, go to Cadence User Registration and complete the requested information.

Hungry for Training? Choose the Cadence Training Menu that’s right for you.

 Training Bytes

UVM-MS Architecture (Video)

Xcelium Simulator Multi-Core Flow (Video)

Blogs

Training Insight: Unlocking the Power of the Xcelium Logic Simulator - Verification - Cadence Blogs - Cadence Community

Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X - Corporate News - Cadence Blogs - Cadence Community

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug - Corporate News - Cadence Blogs - Cadence Community

Please see course learning maps a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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