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In PCI Express (PCIe), a high-speed serial computer expansion bus standard, Compliance mode is used for testing the transmitter and interconnect to assess if their voltage and timing are compliant with the specification. This testing happens in the Polling Compliance state which is a dedicated state for Compliance testing in the Link Training and Status State Machine (LTSSM). In Unraveling the PCIe.6.0 Compliance Feature, we discussed more on how the compliance feature works.
A pattern of bits is sent by the PCIe device, which allows it to measure the inter-symbol interference (ISI) and crosstalk. There are two modes of operating that require different patterns: the Normal mode, which is used with a compliance load board (CLB) or compliance base board (CBB) and oscilloscope, and the Modified mode, which supports inter-operability testing used with testing and measurement equipment like a pattern generator, bit error rate testers (BERTs), oscilloscope, etc.
Along with the compliance patterns differing in Normal and Modified mode, the compliance patterns are also different in non-block mode (Gen1/Gen2) and block mode (Gen3+).
A PCIe re-timer is a component that improves the signal quality of a PCIe link by retransmitting the physical layer signals it receives. It is allowed for the re-timer to lock leisurely on the incoming compliance patterns it receives and retransmit them to the peer PCIe device. Being allowed the leisure to lock on the incoming compliance pattern received, the re-timer can therefore retransmit truncated and skewed compliance patterns towards the end peer PCIe device.
Truncated and skewed compliance patterns pose severe test verification challenges in Normal Non-Block mode due to the nature and repeated sequence of symbols (COM) present in them and the fact that the receiving PCIe device relies on COM symbol to achieve symbol lock. Truncated compliance patterns are not an issue for Block Mode since it consists of distinct electrical idle exit ordered sets (EIEOS), which occur once within several other symbols for each compliance pattern, giving the receiver PCIe device enough time to lock.
Normal non-block compliance patterns consist of repeated COM symbols as seen in the matrix below, which make it hard to identify the beginning, middle, or end of Normal non-block mode compliance patterns. In addition to this, a re-timer might take time to lock on the received compliance pattern and, therefore, start forwarding it in its middle, on separate times and on different lanes. To add to the complexity, there are two varieties of compliance patterns in non-block mode, namely normal and modified compliance patterns, containing multiple COMs. Add to this the varying skews used by the re-timer in non-block mode.
The receiving PCIe Verification Intellectual Property (VIP) might lock in the middle of the compliance pattern received from the re-timer design under test (DUT), giving the impression that the compliance pattern is identified, but leading to errors later during the simulation. As seen below, the highlighted green box is the accurate COM to lock on, while the red box is the inaccurate one.
Locking to the accurate compliance pattern from the truncated ones received on different lanes at separate times under skew are essentially the compliance test verification challenges that the receiving PCIe device needs to deal with.
Cadence VIP for PCIe not only overcomes the above challenges, but far exceeds them by locking accurately on truncated normal compliance patterns, allowing checkers and counters on them, and supporting more skew than spec permitted. Cadence VIP for PCIe can support eight symbol skews for Gen1 and Gen2, whereas spec allows only five symbol skews for Gen1 and four symbol skews for Gen2. All this is available by enabling a simple configurable compliance setting provided as part of the application programming interface (API) to the customer. This feature has been successfully deployed and has helped customers verify their re-timer DUT.