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The demand for intelligence is spreading technology into verticals such as automotive, healthcare, etc., leading to more convenience, luxury, and semiconductor growth. For reliability and efficiency, designers/OEMs must ensure that such devices consume less power and remain functional for longer durations.
Remember when the phone lasted for 27 minutes or while using the camera message flashed "device is shutting down due to heat." Now, imagine how safety-critical devices like pacemakers, wearables, etc., need long runtime on a single charge. It is essential to carefully analyze the power consumption to avoid errant operations.
Several power estimation schemes and tests are conducted to ensure the operation's low power consumption and reliability. Designers face many challenges while estimating actual dynamic power; it becomes more critical as we move below 14nm as a significant portion of dynamic power results from glitches. The Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms captured by Palladium® emulation onto a timing-annotated gate-level netlist for creating glitch-accurate waveforms of multi-billion gate SoC designs.
These glitch-accurate waveforms can be used by the power estimation tool deployed by the user to get highly accurate dynamic power estimation. The Cadence Xcelium PowerPlayback helps to estimate the dynamic power estimation more correctly and gives user the ability to replay the original 0-delay waveforms (Palladium) and reconstruct the glitch-switching activities on signals/nodes of the Netlist. Palladium's Dynamic Power Analysis (DPA) capabilities enable users to analyze power trends over very long emulation runs to identify time intervals for more accurate glitch-based power analysis.
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Static power dissipation is due to the leakage current drawn from the supply and is also referred to as leakage power as it is the power that leaks when the device is turned off. CMOS devices have extremely low static power dissipation.
Dynamic Power depends on the switching activity in the circuit. The accuracy of dynamic power estimation depends on how faithfully the switching transitions are captured.
Pdynamic = PSwitching + Pshort Circuit + PGlitch
Switching power is expressed as the power dissipated by charging/discharging of load capacitance of the output cell.
Pswitching = V2dd*α*CL*f
Here, Vdd is the supply voltage, α represents the switching activity, which means the probability of the gate having 0 1/10 transitions, load capacitance CL, and f shows the frequency of operation.
The short circuit power results from power dissipation during the small-time period when both the MOSFETS are ON
PShortCircuit = IShortCircuit * Vdd
Glitch power is the result of glitches causing the output of the gate to transition to an intermediate state, and the power consumed during these glitches is called glitch power.
PGlitch = FGlitch *CL* V2dd
Here, FGlitch represents the average frequency of glitches. In advanced process node chips, glitch power may occupy a significant fraction, up to 20~40% of the whole dynamic power consumption in various scenarios. Glitch power analysis flow is as under.
Cadence has dedicated tools (Voltus/Joules) to generate detailed power analysis reports. While to get accurate power data, precise waveform inputs are critical. Simulation waveforms are used for dynamic power analysis. However, extensive design simulation is not efficient.
To address these challenges, we need a solution that can help us leverage zero-delay activity vectors to derive relevant activity vectors that also capture glitches.
Cadence offers the "Xcelium PowerPlayback" app to address such issues for accurate power analysis with the ability to reconstruct the delays in waveforms. It is used for SDF annotated netlist power analysis or early RTL power exploration.
Only essential signals (PI, DFF's outputs, Macro output) are played every cycle, and the transitions on the essential signals propagate through SDF annotated combo logics, thus reconstructing glitches.
Here, the waveform is captured and replayed at the gate-level Netlist. The input captured netlist waveform has complete design dumped. However, PowerPlayBack replays only key node signals. All this information is already contained in the Delay file provided, and the tool can automatically extract them.
The Xcelium PowerPlayback can replay the captured RTL waveform to its equivalent Netlist, as long as the RTL-vs-Netlist mapping file is provided, where it can automatically extract the essential signals (primary inputs, DFF outputs, memory/macro outputs) from the mapping file, then replay them from RTL waveform to paired netlist signals.
To maximize the runtime performance, PowerPlayBack can automatically split one whole Captured time window into small segments and replay them in parallel. After the replay, all the output SHM waveform segments can be stitched together as one entire SHM waveform file to deliver.