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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi…

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog…

• 3 min read
SystemVerilog , uvm , multi-language verification , UVM Scoreboard , verification

DAC 2015 – Join Us to Experience the Continuum of Verification and System Development…

The biggest yearly event in electronic design automation (EDA) is due to take over…

• 8 min read
cadence , EDA , Moscone Center , DAC 2015 , verification , system development

It’s Time to Modernize Debug Data and It’s Happening at DAC

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog…

• 2 min read
Verdi , debug , simvision , VCs , Indago , Debussy , Questa , Incisive Enterprise Simulator (IES) , IES

How Ethernet Standards Are Born

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to…

• 5 min read
Verification IP , 802.3bp , Ethernet standards , Automotive Ethernet , Ethernet , 802.3 , Marris

Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using…

In the previous blog post , we created a simple multi-language verification environment…

• 3 min read
IEEE 1647 , uvm , methodology , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Multi-Language Verification Environment—Getting First Run in Few Minutes

Seems that by now, every one in the industry realizes that multi-language verification…

• 2 min read
uvm , methodology , e , e language , UVC , multi-language

Specman deep_copy()—Creating Too Many Structs

This blog starts with a description of a debugging session of a mysterious behavior…

• 3 min read
Specman , debug , e , Funcional Verification , ClubT

Indago Protocol Debug and IP Verification

Nothing beats knowing, a late electronics-industry veteran used to say. That’s no…

• 3 min read
IP , cadence , debug , Functional Verification , electronics system design , Indago , engineering , verification

Don’t Lose Extra Simulation Cycles

After reading the rest of this blog, you might guess the truth, which is that my…

• 2 min read
Specman , e , e verification code , simulation , verification

Deque to the Rescue—Introducing the e Template Library

A customer working on a VIP component identified that the performance of one of their…

• 4 min read
e Template Library , e , FIFO , eTL , deque

Double-Take: Power Event Monitoring and In-Circuit Acceleration

For a number of years now, AMD has been applying an advanced acceleration use case…

• 1 min read
power event monitoring , Verification Computing Platform , system-level validation , hybrid verification , hardware assisted verification , Palladium XP , Emulation , in-circuit acceleration

Heading Off the Butterfly Effect—The SimVision "Quick Diff"

Functional Verification Debug Blog - SimVision Gems Most engineers are familiar…

• 1 min read
HDL , "butterfly effect" , SimVision waveforms diff , Verilog , SimCompare , VHDL

Dealing with the "Throw it Over the Wall" Methodology in Power Supply Network De…

"Throw it over the wall" is business slang for completing your part of a project…

• 2 min read
PSN , Power Supply Network , debug , Functional Verification , power-aware , UPF

Searching Through a Complex Design? DFS to the Rescue!

Recently, while at a customer site, I was faced with the huge task of looking for…

• 4 min read
Functional Verification , simvision , design file search , Incisive Enterprise Simulator (IES)

Lazy Test Cases for Tool Failures Using the Testcase Optimizer (TCO)

The Current State It seems to be a fact of life that software has bugs and, unfortunately…

• 7 min read
performance , methodology , verification strategy , debug , tech tips , Incisive , universal verification methodology , verification

Using Generative List Pseudo Methods in Constraints – A Case Study

This article highlights the use of list pseudo-methods constraining the content of…

• 2 min read
Specman , list pseudo-methods , Ethernet , constraint coding , debugging

Connected Field Sets – What Are Those and Why Should I Care?

Right form the start Specman has been very good at generating constrained random…

• 4 min read
connected field sets , Specman , modeling constraints , IntelliGen constraint solver , Constraints , debugging

Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the…

• 1 min read
funtional verification , SystemVerilog , UVM-ML , UVMWorld , UVM multi-language , e , SystemC

Code Coverage at the System Level with Hardware-Assisted Verification? Are You Kidding…

Short answer: Nope, not kidding. You can get value from applying code coverage with…

• 2 min read
hardware-assisted verification , code coverage , functional coverage , verification closure , verification

Dealing with Specman-Simulator Interface Issues—Get Ready to Cook!

Two great documents, aiming to make life easier for a verification engineer, were…

• less than a min read
Specman , debug , Functional Verification , Incisive , e language , simulation

Time to Play - You Can Now Run Your e Code on EDAplayground

Over the years I've often hoped to have the ability to show someone (a customer,…

• less than a min read
IEEE 1647 , Functional Verification , tech tips , EDA , e language , team specman , Aspect Oriented Programming

Code Coverage at the System Level with Hardware-Assisted Verification (Part II)

In yesterday’s Part I blog post , I talked about a technique for focusing code coverage…

• 4 min read
hardware-assisted verification , code coverage , system-level code coverage , coverage analysis , functional coverage

Where Is the Money for IoT?

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which…

• 1 min read
Verification IP , DSP , IP , IoT , Tensilica , always-on

Generic Dynamic Runtime Operations With e Reflection - Part 3: Additional Capabilities…

This post concludes the series of blog posts that discuss the dynamic capabilities…

• 3 min read
AF , Specman , debug , Functional Verification , Incisive , e language , reflection , simulation

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture…

• 5 min read
AF , uvm , Specman , debug , Functional Verification , Incisive , UVM ML , e language , simulation

Generic dynamic run-time operations with e reflection Part II

Field access and method invocations In the previous blog , we explained what are…

• 4 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Looking Back at a Great Week for System Design!

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had…

• 3 min read
debug , System Design and Verification , embedded software , hybrid , ARM TechCon 2014 , ARM , verification

Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

In its 10th year now, ARM TechCon is in full swing this week at the Santa Clara Convention…

• 3 min read
NVIDIA , Palladium , hybrid , Emulation , ARM Fast Models , ARM
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