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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection…

• 5 min read
virtual prototypes , IP integration , abstraction , VCC , VSI , IP assembly , cars , EDAC , software , automobiles , 1997 , Virtual Platforms , IEEE Spectrum , Schirrmeister , ESL , ESL system-level design

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level…

• 2 min read
verification speed , whitepaper , uvm , Low Power , gate level , simulation speed , Functional Verification , Incisive Enterprise Simulator , 20nm , Low-Power , Incisive , Mixed-Signal , gate-level , Incisive performance , Simulation acceleration , DVcon , testbench , Incisive Enterprise Simulator (IES) , simulation , IES , Assertion-based verification , IES-XL

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification…

• 1 min read
SystemVerilog , uvm , Functional Verification , UVM e , UVM-MS , 20nm , Low-Power , Incisive , Mixed-Signal , multi-language , Acellera VIP TSC , mixed signal , MDV , IES , VMM

Video Killed the Reference Manual Star

[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star…

• 1 min read
ABV , videos , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , YouTube , SVA , PSL , assertions , Axel Scherer , MDV , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with…

Right before the December holidays it was my privilege to host the first "Club Formal…

• 3 min read
uvm , Vincent Reynolds , ABV , Joerg Mueller , metric driven verification (MDV) , ABVIP , coherency , assertions , Club Formal , UK , MDV , Bob Kurshan , Assertion-based verification

2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence…

• 4 min read
Intel , DAC , Joe Hupcey III , OLED 3D , TV , Consumer Electronics Show , Formal Analysis , CES , formal , 14nm , EDA360 , CES2012 , OLED , DVcon , apps , ARM , LG

Creating the Zynq Virtual Platform, Including Errata

Although I have never contributed any code to the Linux kernel, the headline We are…

• 5 min read
Virtual System Platform , virtual prototoypes , zynq , virtual platforms , IP-XACT , errata , embedded software , SystemC , linux , Embedded Linux , System Design and Verification

Video: Bob Kurshan, Cadence Fellow and Incisive Formal R&D Leader, talks about Formal…

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
ABV , Formal Analysis , formal , video , Kurshan , cache coherency , IEV , Bob Kurshan , Formal verification , IFV , verification , Assertion-based verification

Ubuntu Updates for 2012

I'm overdue to provide an update on how to run Virtual System Platform (VSP) and…

• 6 min read
Virtual System Platform , zynq , GDB , VSP , Incisive , Ubuntu , VirtualBox , SystemC , Virtual Platforms , System Design and Verification

TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design…

• 5 min read
High-Level Synthesis , ASIC , TLM , system realization , C-to-Silcon , TSMC , system design , SystemC , Hardware/software co-verification , HLS , C++ , verification

Free Formal and ABV Webinar Recordings from 2011 Online Now!

In case you missed any of the 5 free webinars Team Verify presented in 2011, you…

• 3 min read
NextOp , scoreboard , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , BugScope , Incisive , ADS , coverage driven verification (CDV) , SoC Connectivity , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

One Oil Change and Update my Car to the Latest Software Patch, Please!

Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my…

• 3 min read
Automotive , virtual platforms , edaForum , Infineon , V-Diagram , virtual prototypes , ECU , Bosch , System-Level Design , Freescael , Design Flows , embeded software , Engine Control Unit

Some Final Real-World Assertions for the Holidays

My last "real-world assertions" blog post seems to have tickled a bunch of people…

• 3 min read
holidays , ABV , Functional Verification , assertions , real-world assertions , Assertion-based verification

Video: Incisive Formal Verifier R&D Leader Pradeep Goyal talks about Expert Formal…

Continuing the series that introduces you to the people that create the tools you…

• less than a min read
Pradeep Goyal , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , Model-checking , formal , Incisive , assertions , Formal verification , IFV , verification , Assertion-based verification

High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers…

• 1 min read
High-Level Synthesis , control-dominated , CDNLive , C to Silicon , Freescale , control , SystemC , CDNLive! , HLS , FPGA , System Design and Verification

Equine Anatomy, Pax Romana and the Reach of Standards

At the recent Synopsys EDA Interoperability Forum, the opening session focused on…

• 5 min read
pax romana , IP , markets , virtual platforms , TLM , horses , Acceleration , Standards , OSCI , Hogan , embedded software , Magarshack , Goodenough , system design , system , Accellera , Jim Hogan , SoC Realization , SystemC , interoperability , high level synthesis , ESL , architect , System Design and Verification

Early Holiday Present: Sudoku Solver Using Incisive Enterprise Verifier (IEV) and…

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present…

• 1 min read
ABV , Joerg Mueller , formal , simvision , Sudoku , ADS , PSL , IEV , Assertion-Driven Simulation , Formal verification

Report on ARM Techcon 2011: Real and Virtual Software Apps, High-Speed Silicon and…

The acid test of any conference is how long the information and lessons learned linger…

• 4 min read
ARM Techcon , Charbax , Joe Hupcey III , Virtual System Platform , Richard Goering , 20nm , 14nm , EDA360 , VSP , YouTube , Lego , robot , Chi-Ping Hsu , ARM , Steve Leibson , Jason Andrews , Rubik's Cube

Embracing Our Competitors with the Connections Program

In my last blog post , I described the Cadence Verification Alliance (VA) and how…

• 2 min read
NextOp , collaboration , Zocalo , Functional Verification , partnerships , VA , VIP , EDA360 , Duolog , verification alliance , Connections , interoperability , verification

Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run…

• 2 min read
uvm , OVM , Incisive Enterprise Simulator , Accellera VIP TSC , UVM training , IES , IES-XL

Secrets of the (Verification) Alliance

In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially…

• 3 min read
uvm , collaboration , Specman , Functional Verification , VAalliance , partnerships , VA , VIP , EDA360 , EDA , Verisity , verification alliance , Doulos , AMIQ , Oski , verification

Video: Meet Incisive Enterprise Verifier R&D Architect Vinaya Singh

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
Joe Hupcey III , ABV , Vinaya Singh , Functional Verification , Formal Analysis , formal , video , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update…

• 2 min read
uvm , IP-XACT , Functional Verification , OVM , Register Package , Incisive , IES , OVMWorld , verification

Video: Meet Formal and ABV R&D Team Leader Deepak Pant

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer…

• less than a min read
Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Deepak Pant , video , ADS , assertions , IEV , Formal verification , IFV , Assertion-based verification

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

During the planning phase for SoC designs, teams have to choose whether to "make…

• 2 min read
High-Level Synthesis , IP , TLM , System Design and Verification , C-to-Silcon , IP re-use , re-use , reuse , SystemC , C-to-Silicon Compiler

Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create…

• 3 min read
zynq , edaForum , virtual prototypes , industrial , System-Level Design , Siemens , Virtual Platforms , Industrial Automation , Design Flows , Sanitas

India Needs Real-World Assertions Too

I've just returned from a week-long trip to India, spending most of my time at the…

• 4 min read
Functional Verification , Old Delhi , Noida , assertions , New Delhi , real-world assertions , India

Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile…

• 3 min read
Virtual System Platform , virtual platforms , GNU , parallel compilation , virtual prototypes , embedded software , C , LSF , compile , pallallel compile , make , SystemC , System Design and Verification
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