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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Comment Direct From XJTAG, Ltd.

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their…

• 2 min read
DAC , Functional Verification , XJTAG

Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 6 min read
IntelliGen , Specman , debug , Functional Verification , e , AOP , IES-XL

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System…

One of the great things about DAC is the opportunity to meet new people and find…

• 2 min read
DAC , System Design and Verification , Incisive , SoC , Marvel

Survey Results and Commentary on The XJTAG Girls at DAC 2009

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls…

• 7 min read
DAC , Functional Verification , OVM , XJTAG

More Details on Post Silicon Embedded Software Verification With ISX

Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in…

• 3 min read
AXI , eVC , System Design and Verification , OVM , SoC , ISX , ARM , ESL , FPGA

Slides From DAC Virtual Platform Workshop

As a follow-up to my report on the DAC Virtual Platform Workshop I would like to…

• less than a min read
DAC , virtual platform , System Design and Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype

Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle…

Being a Brit, Cricket is never very far from my thoughts especially when travelling…

• 2 min read
Intel , Low Power , System Design and Verification , embedded software , ARM

Post-DAC 2009 Survey on The XJTAG Girls

One non-technology item that received an extraordinary buzz at DAC 2009 were the…

• 1 min read
DAC , Functional Verification

1st Ever Virtual Platform Workshop Deemed a Success

Yesterday DAC hosted the first ever Virtual Platform Workshop , a full day dedicated…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification

Finding the Opportunities in ESL

I came to DAC 2009 looking for the industry trends in ESL, because as we all know…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification , ESL High Level Synthesis

Day 1 of DAC is a Wrap

Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis…

• 3 min read
DAC , TLM 2.0 , System C , OSCiI , System Design and Verification

Customer Questions About TLM-driven Design and Verification

In the latest blog published by Ron Wilson there were two questions about our TLM…

• 1 min read
System Design and Verification , TLM 2.0 , System C , C-to-Silicon , high level synthesis

DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able…

• 1 min read
DAC , IntelliGen , Specman , Functional Verification , simvision , OVM e , e , SystemC , IES-XL

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some…

• 1 min read
SystemVerilog , debug , Functional Verification , simvision , Verilog , IES

DAC '09 for the Specmaniac

The following are the "must see" items for Specmaniacs lucky enough to get travel…

• 3 min read
DAC , Specman , Functional Verification , OVM e , e , Mike Stellfox , Jason Andrews

At DAC Next Week

Yours truly will be at the big show next week, and I hope that all of you in the…

• 1 min read
DAC , Specman , Functional Verification , OVM , OVM e , DVcon

Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage…

• 2 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

It's DAC Time Again!

By now, you've probably seen that Cadence is participating quite heavily in DAC this…

• 2 min read
DAC , Functional Verification , verification

Specman And The Cadence ESL+TLM News

Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification…

• 2 min read
IEEE 1647 , DAC , Specman , TLM , Verification methodology , Functional Verification , simvision , OVM e , e , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , ESL , AOP , IES-XL

What is Next for SystemC?

Let your voice be heard at the North American SystemC Users Group interactive Town…

• 1 min read
TLM , System Design and Verification , OSCI , SystemC , high level synthesis , HLS

The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume

" Tackling formal assumptions through verification planning " is a recent article…

• less than a min read
funtional verification , ABV , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , Incisive , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV) , Functional Verificatioa , verification

North American SystemC User's Group Co-Located at DAC 2009

We've been hearing about SystemC for a while. It's a great language! What's it great…

• less than a min read
OSCI , Analysis , SystemC , NASCUG , System Design and Verification

Write Right OVM Verification Components

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes…

• 4 min read
SystemVerilog , OVM ML , OVM e , OVM SV , OVMWorld

TLM-Driven Design and Verification Solution

At this week's CDNLive! Japan we made an important press release announcement about…

• 2 min read
TLM-driven design , Calypto , Incisive , System C , TDM , C-to-Silicon , ARM , System Design and Verification

Tips on Using e Macros to Raise Abstraction and Facilitate Reuse

[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.] …

• 5 min read
IEEE 1647 , Specman , Functional Verification , tech tips , e , team specman , macros , Incisive Enterprise Simulator (IES) , IES-XL
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