Analog, RF, and Photonics into One System: The Best Way to Integrate

Modern Chip Architects are balancing more demands than ever as they design whole systems, which is a lot more than just designing a digital chip. They must consider analog, radio frequency (RF), photonics, advanced packaging, signal integrity, connectors, complex chiplets, and barely routable circuit boards. These modern architects must figure out the best partitioning to achieve the power and performance required.

No longer can Chip Architects ask designers to use a combination of different tools to design these various parts of the system. Instead, design teams need an advanced methodology to design systems that are low power, incorporate increasing fractions of analog, RF, and photonics, and require flexibility to change process notes and packaging. Above all else, this advanced methodology must utilize shared databases. When tools don’t share databases, design can be slow and inefficient. Additionally, each time the data format is transformed, there is a loss of accuracy.

Finally, there are tool sets that answer these challenges on a system level:

1. Drive up the level of abstraction. RF design can be done in RF terms, not polygons. Photonics designs can be done at a high level, so the designer doesn’t have to worry about the precise shape of every unit. Analog productivity increases with added automation, so analog design is done at the specification level. Circuit simulation performance is improved because it is key to everything outside of digital design.
2. Drive down the level of detail, since otherwise, noise becomes a huge problem with EM emissions and interference, thermal, traces, connectors, cables, antennas, and signal integrity in chips, packages, and boards.
3. Allow different parts of the chips to be designed in the best possible ways. Whereas the digital and other high-performance subsystems can be implemented on the latest and greatest process technology, analog and RF is often best designed on older, proven process nodes. Chiplet-to-chiplet communications must be seriously considered.
4. Increase the level of automation and integration so that there are suites of tools built on common databases with common semantics and engines to avoid inaccuracies. Packaging and PCBs need to be co-designed, and the whole system needs to be analyzed for thermal interactions.

What are the requirements for a mature, trustworthy mixed-signal tool solution? Look for a vendor that lets the teams:

1. Boost custom and analog advanced-node design productivity with targeted place and route automation techniques, accelerating the layout implementation of the most advanced nodes using row-based methodology and multiple pattern technology (MPT).
2. Analyze electromigration and IR drop with electrically aware design that lets the team monitor electrical issues as the layout is created to avoid multiple design iterations and “over design.” It’s important that the tool facilitates the understanding of subnet current flow, allowing for correct wire sizing without excess parasitics.
3. Drive layout implementation with simulation-driven routing (SDR) intelligence. Correctly size every net segment and via using a SDR engine.
4. Efficiently model passive components with an integrated electromagnetic solver that quickly and accurately simulates high-frequency and RF circuits.
5. Divide and conquer with concurrent layout editing, allowing the team to work on large layouts together for faster layout implementation, chip finishing, and routing.
6. Accelerate floorplanning and optimize routability with design planning and analysis that helps create optimal floorplans combining top-down and bottom-up methodologies with congestion-aware hierarchical pin placement.

These are just some of the biggest challenges for system designers.

Every design is different, but most system architects are facing these issues:

1. Copper is being used less and less, and signals are moving to photonics (data centers) and wireless. These require analog/mixed-signal design and RF design if wireless.
2. Systems are increasingly being packaged in advanced 3D packaging. This allows new and attractive forms of integration where the analog and RF parts of the design can be constructed in the “best” process generation for the design, rather than having to make do with whatever analog capabilities, often limited, are available in the advanced node being used for traditional system-on-chip (SoC) integration.
3. Low power is a top-level imperative for every design. For battery-powered devices, this translates directly into an attribute that the consumer cares about – battery life. For chips in data centers, the power used by the electronics plus the power required to get all the heat out again can equal the cost of the servers and routers.
4. Cars are loaded with sensors that typically require analog interfaces.
5. Companies are increasingly paying more than lip service to sustainability goals, and one of the best places to attack is reducing power across the board. From power electronics to RF circuits to optical – all have parts to play in doing this.
6. Companies increasingly want to manufacture designs in multiple foundries due to supply constraints. Some companies could grow faster, but they cannot get enough silicon in the process node for which the parts were originally designed. Companies need to quickly transition designs to new foundries and process nodes.

System design is incredibly complex and requires an intelligent approach. Look for tools that help manage the entire process. With an interoperable collaborative design approach where all the teams can work together, sharing design data and information to reduce iterations and improve overall efficiency and turnaround time.

To learn more about how to solve these system design issues, read here. (link to https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/isd-and-analog). Here’s more information on mixed-signal design (link to https://www.cadence.com/en_US/home/solutions/mixed-signal-solutions.html).