Start Your Engines: Pointers to Speed Up a Slow Mixed-Signal Simulation

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

There might be times when the mixed-signal verification engineers observe a slow analog mixed-signal (AMS) simulation. The complexity of design and inappropriate usage of simulator options may be the causes of this slowness. The pressure to timely market the chip makes the mixed-signal simulation performance an important and obvious parameter that every SoC functional verification engineer should consider.

There can be multiple factors that can hamper the mixed-signal simulation performance. Let us review some such factors in this blog.

The mixed-signal simulation performance issues can be broadly categorized into two areas:

• Design, models, or testbench related
• Simulator and hardware resource related

A seasoned mixed-signal verification engineer would investigate both these aspects and optimize the design, testbench, simulator, and its options along with proper hardware to run the simulation.

Addressing design/models/testbench-related issues

Verification engineers should choose a correct mix of functional definitions (Post-layout SPICE with SPF/DSPF, SPICE, Verilog, SystemVerilog, Verilog-A/AMS, Real/Wreal model) in an individual block to test the functionality within a given timeline and coverage. The analog solver in a mixed-signal simulation can become a performance bottleneck because the analog solver is time step-based, whereas a digital solver is event-based. Therefore, verification engineers should be careful while selecting the analog blocks for a functional mix, especially the block with parasitics. Verification engineers should report inefficient models to the modeling engineer based on the information available in the simulator log file.

The art of reusing the existing compiled snapshot or saved state for multiple runs will also save a lot of verification time.

Addressing simulator-related issues

Based on the design type and functional definitions used in design, the verification engineer should choose the correct analog solver and solver option. The thing of utmost importance is to use correct simulator settings to optimize the simulation run as per the speed and accuracy requirement. You must ensure that the simulator settings result in minimum A2D and D2A conversion events during the run. Parasitic optimization techniques, accuracy settings, usage of pre-compiled standard libraries, choice of SPICE/FastSPICE solver, multi-threading are also some of the factors to consider for reducing the run time.

For more information on debugging a slow AMS Designer simulation, refer to the How to debug slow AMS Designer simulation article on Cadence Support portal.

Lalit Mohan

Related Resources

• One-Stop Knowledge Resource for Mixed-Signal Verification
• Spectre AMS Designer Product Page

For more information on Cadence circuit design products and services, visit www.cadence.com. 

About Start Your Engines

The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.