Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

The SystemVerilog (SV) Testbench technology with UVM (Universal Verification Methodology) offers many advantages in stimulating, monitoring and verifying mixed-signal designs. Until recently, this was only considered for pure digital functional verification.

With the addition of the new Virtuoso Advanced Testbench Reuse flow with Xcelium, complex stimulus and monitoring capabilities of a SV UVM testbench are easily reused in the AMS UNL (AMS Unified Netlister) flow without the hassles of importing the testbench, packages, and setup files into the Virtuoso environment. This makes the SV testbench reuse methodology almost impossible to pull off, until now.

The idea behind this new methodology is to implicitly overlay the SV UVM bench over the existing Virtuoso schematic thus allowing the reuse of the SV stimulus in place of the original schematic stimulus. The Virtuoso user continues to run the simulation in their ADE environment exercising the AMS UNL version of the DUT (Device Under Test) with the same constrained randomized stimulus that verified the digital abstraction of the DUT. 

This accomplishes two things. 

One, the ability to stay with one, shared testbench between the analog and digital verification teams so as to achieve consistent functional sign off results. Second, the idea of carrying over the concept of functional coverage to the analog world by reusing what the digital verification world confidently signs off with everyday. The UVM tests and coverage metrics enable metric-driven automation to functionally sign off the AMS UNL configuration with confidence. 

If you’re interested in learning more about what Cadence has to offer in this space, check out the Virtuoso Advanced SV UVM Testbench Reuse Flow Rapid Adoption Kit.

Rick Sanborn

Related Resources

• One-Stop Knowledge Resource for Mixed-Signal Verification
• Spectre AMS Designer Product Page

For more information on Cadence circuit design products and services, visit www.cadence.com. 

About Start Your Engines

The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.