Start Your Engines: Seven Habits of Highly Efficient Mixed Signal Verification Engineers

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

Mixed-signal verification is a very complex and time-consuming task. It needs advanced state-of-the-art complex solvers and massively powerful computational resources. A mixed-signal verification engineer is required to balance the time-to-market pressure with the appropriate coverage and accuracy of simulation results. In this blog, I will share seven best practices that every mixed-signal verification engineer should follow.

The figure shown above represents a typical low power mixed-signal System-on-Chip (SoC). It also shows the complexity of the AMS implementation and verification environment.

Habit 1: Use correct mix of functional definitions for each block

System verification starts much earlier than block implementation. This is a key feature of the top-down design methodology. Blocks are written initially in high-level design languages (HDL) like Verilog, SystemVerilog, System C, VHDL, Verilog-A, Verilog-AMS, and Real models. The simulation performance of blocks written in HDLs is much better than the corresponding transistor-level implementation (with and without post-layout). It is impossible to run a system-level simulation of a complex SoC with all blocks that have transistor-level implementation (with post-layout parasitics) within a practical timeline.

A verification plan consists of multiple cycles of simulation, and if not put together correctly, it could require a few months to a couple of years to complete. Therefore, it is important for verification engineers to use a correct mix of the functional definitions of each block for individual runs. This helps in completing the simulation in reasonable time. For example, the PLL simulation at transistor level with parasitic takes a longer simulation time. Hence, when you simulate PLL at transistor level, you can use the HDL definition for other blocks wherever possible. In addition, it is essential to identify the blocks with longer runtime in the design to meet the verification timeline with an appropriate coverage. You should also consider the design-critical timing path and accuracy requirements for choosing the correct functional mix.

Habit 2: Maximize automation scope

Most verification engineers use automation to validate results. They also use automation to create scripts, testbenches, stimuli, and so on. However, there are still certain tasks that currently require manual effort. For example, consider analog and digital IP verification environments. Analog IPs are developed inside the GUI-based environment, while digital IPs are developed in the command-line/UVM environment. When an IP is imported from one environment to another, it is a manual process. Another example can be the verification coverage reports – as the analog and digital domains have different mechanisms to handle the simulation coverage. It is hard to bring simulation results from one environment and update the coverage report in another.

Cadence provides the tools to automate these manual tasks. IPs can easily be ported within different environments. Coverage can be also be monitored at a common place where analog and digital verification environments communicate. Cadence solutions like Virtuoso ADE Verifier to vManager connection and CLIPS and Virtuoso IP re-use are two such examples.

Refer to the following rapid adoption kits (RAK):

• Virtuoso AMS IP Reuse with CLIPS(Command-Line IP Selector) for hands-on examples on CLIPS.
• Virtuoso Advanced SV UVM Testbench Reuse Flow for hands-on examples on the Virtuoso advanced Testbench Reuse flow.
• Virtuoso ADE Verifier – vManager Connection for hands-on examples on Virtuoso ADE Verifier to vManager connection.

Habit 3: Reuse captured data (snapshots, saved Simulation states, and so on)

A mixed-signal simulation consists of three steps; compilation, elaboration, and simulation. A seasoned mixed-signal verification engineer would save time invested on all these steps for multiple runs wherever possible. Advanced EDA tools like Cadence Xcelium and Spectre suite of simulators provide features like Multi Snapshot Incremental Elaboration (MSIE), Process Based Save Restart (PBSR), Reuse of Analog HDL compiled libraries, and Analog Solver Save Restart to help mixed-signal verification engineers to speed up the verification task. These features help verification engineers save a lot of time spent on compilation, elaboration, and simulation. Using these features, the simulation performance can improve by 2x-10x depending upon the usage scenario. Use Cadence technologies like MSIE, PBSR, and Spectre Save-Recover to improve verification time.

Refer to the following articles for more information about the technologies mentioned above. 

• One-Stop Knowledge Resource for MSIE (Multi-Snapshot Incremental Elaboration)
• Process Based Save Restart (AXUM Flow)
• Using Spectre Save-Recover

Habit 4: Choose analog solver wisely

In mixed-signal simulations, the performance bottleneck comes from the analog solver because the analog simulation is variable-timestep-numerical-method-based simulation unlike the digital simulation, which is event-driven. At different verification stages, you have different mixed definitions for blocks. Hence, the choice of the analog solver for a specific run depends on the functional mix of blocks for a run.

Refer to the following articles for more details on Cadence SPICE solvers: 

• Introducing Spectre X
• Optimizing Spectre APS Performance
• Spectre FX

Habit 5: Extract most out of analog and digital solvers to optimize performance and accuracy

Tuning analog solver is the most important step in mixed-signal verification. It needs a good amount of experience and command on the analog solver usage. An analog solver provides a lot of options and arguments to control the algorithmic behavior of the solver on different parts of a design. EDA tool vendors provide some existing presets and direction guidelines to mine most out of the analog solver. Some common presets and options are as follows:

• Conservative (preset)
• Moderate (preset)
• Liberal (preset)
• Reltol
• Vabstol
• Iabstol
• Post-layout reduction presets/speed
• Circuit Element Optimization options (rshort, dcut, ccut, and so on)
• Relative signal reference
• Max step

Refer to article, How to debug slow AMSD simulation, to learn methods to improve the simulation speed with desired accuracy.

Habit 6: Save data wisely to reduce I/O data writing time

The mixed-signal simulation takes a significant amount of time in data writing because the process involves I/O interactions. The execution host is generally different from the filer machine (where result data is saved). Apart from saving data, smart EDA tools compress the data before saving it to improve disk usage. Compression of the result databases also takes incremental time in addition to time spent in data writing. To reduce data-saving time, Cadence Spectre AMS Designer provides a new data-saving mechanism in the Flex mode where digital and analog solvers write data in parallel, eventually reducing the overall simulation time. Although EDA tools are being improvised to optimize data writing, an experienced mixed-signal verification engineer will only save signals of interest. There is no point saving millions of nodes in the design unnecessarily. There are ways to filter individual net fragments for post-layout blocks. In addition, there are options available to save certain signals for a specific duration of simulation time. If you want to interactively analyze selected signals (voltage or currents) during simulation time, you can use an intelligent and interactive debug feature like SimVision MS (Mixed Signal).

Refer to the article, Optimizing disk space efficiency for AMS simulations, article for tips to save signals wisely. 

Habit 7: Create a seamless channel with EDA vendors

During verification cycles, some unforeseen scenarios are encountered. The design and modeling teams provide best of their models/design blocks with IP-level testing. Verification engineers put in their best efforts. EDA vendors provide best tools in terms of quality. There can be lot of time delay in NDA approvals and Secure Chamber access. Large semiconductor companies take care of this bottleneck upfront and create a seamless channel with EDA vendors because they know that some unforeseen scenarios might be encountered during the verification cycle. Dedicated support and service offerings are provided by Cadence to help customers succeed. You can contact Cadence Sales team for such engagements.

Refer to the application note, Seven Habits of Highly Efficient Mixed Signal Verification Engineers, to learn more on this.

~Lalit Mohan

Related Resources

• One-Stop Knowledge Resource for Mixed-Signal Verification
• Spectre AMS Designer Product Page
• Using SimVision with AMS Simulator
• Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com. 

About Start Your Engines

The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced understanding of existing features, and much more. To receive notifications about new blogs in this series, click Subscribe  and submit your email ID in the Subscriptions box.