BoardSurfers: Training Insights: Reducing Time to Market with Allegro DesignTrue DFM Checks

Allegro DesignTrue DFM rules help you perform fabrication, assembly, and test checks in real-time while designing your boards. You can add Allegro DesignTrue DFM rules to your design workflow and run them in the early stages of the design cycle. An in-depth understanding of the Allegro DesignTrue DFM rules enables you to leverage the tool and create designs that are successful in the first pass. To help you fully understand the rules that Allegro DesignTrue DFM Technology supports, a new Allegro DesignTrue DFM course has been developed. This blog post outlines how to utilize Allegro DesignTrue DFM checks at different stages of PCB designing.

What are Allegro DesignTrue DFM Rules

Allegro DesignTrue DFM rules determine whether a design is mapped for manufacturability and complies with the manufacturer’s requirements. You set the Allegro DesignTrue DFM manufacturing rules in the Allegro® Constraint Manager. Any violations to manufacturing rules result as DRC errors. These errors need to be fixed before proceeding to the next stage of the layout design.

The first step is obtaining the design rules from the fabrication vendor, which can be done using the DFM Portal. The next step is adding the Allegro DesignTrue DFM rules to the Constraint Manager, which can be done in one of the following ways, based on how the rules are obtained:

• Use DFM Wizard to import the rules, if the rules are obtained as CSV templates
• Import the rules in Constraint Manager using File – Import– Technology File, if the rules are obtained as technology files
• Add the DFM rules manually in the Constraint Manager

The flow described in this post can be customized to suit your needs.

Key DFM Checks to Resolve Manufacturing Issues

The guidelines shared in this post are generic in nature. You can enable specific DFM checks by enabling them in the Analysis Modes dialog box as illustrated in the following image:

The following stages of PCB design can be tested using DFM rules integrated through Allegro DesignTrue DFM technology:

Footprint Creation Stage

Use DFA component lead definition checks to confirm the leads you added to the footprints, such as through holes have sufficient pin-to-hole spacing and SMD pads have sufficient pad sizes to solder. To know more about setting the Component Lead definition, read BoardSurfers: Detecting Potential Component Lead Assembly Issues.

Pre-Placement Stage

After confirming your stackup, add the stackup information to the Cross-section Editor in the layout editor. This information is needed to perform analytic checks, such as hole checks that rely entirely on the stack up information you have added.

Placement Stage

While placing the components, make sure you set the DFA package to package rules in the board file. Violations of spacing between the packages are displayed by DFA circles and DRCs in the design canvas.

The DFA – Pkg to Pkg Spacing rules are specified under Design for Assembly, as the following image shows:

Post-Placement Stage

After the placement and fanout is done, you can run the DFA – Outline checks to perform spacing checks for component-to-board edge (outline) and cutout-to-board edge spacing.

Similarly, you can run the rules DFF – Outline checks to validate the fabricator spacing requirement between the edge of the board and outline of the design objects (etch, pins, and vias) and component-to-board edge and cutout. 

Using the DFT Outline worksheet, you can set the spacing rules between outline and cutout to the test points.

You can also check for aspect ratio violations and annular ring violations to ensure you are in-sync with the manufacturer’s requirements.

Post-Route and Cleanup Stage

After routing, the DFA and DFT worksheets can be used to run the following checks:

• DFA – Spacing checks for component body to pins and vias. You can also run check for traces and vias under specific packages.

         

• DFT – Spacing checks for spacing between test point to pins, vias, holes, and components.
• Copper spacing checks for copper spacing between different objects in a design. Copper spacing checks can be created for the complete design, similar to the spacing rules created as a spacing constraint set (SCSet), to specify minimum copper spacing between different objects in the design. You can create additional spacing rules sets using those CSets and change the spacing rules to look for different violations.    

         

• Copper Features checks for identifying slivers, acid traps, minimum width for traces, shapes, and lines. These checks use maximum shape to pad ratio to measure the copper fill instead of thermals, and also identify issues with antenna traces and vias, thermals, and inadequate spokes.

         

• DFF – Mask, DFF – Annular Ring, and DFA Pastemask checks are used to find issues related to mask slivers, islands, exposed etch, missing solder masks, missing pastemasks, and via pad mask to smd pad mask overlapping issues.
• DFF – Silkscreen checks for finding silk to silk overlaps, silkscreen line length, text, and character width issues.

        

To learn more about DFM rules and using them in the Allegro PCB Editor, enroll in the new Allegro DesignTrue DFM Training. You will learn to create, apply, verify, and fix manufacturing issues when designing a PCB. Additionally, you can learn to add fabrication, assembly, and test constraints and correct fab and assembly issues before sharing the final Gerbers with the manufacturer.

If you find this post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design: 

 Allegro DesignTrue DFM Training 

You can become Cadence Certified once you complete the course.

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