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The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence®. In addition to providing insight into the useful features and enhancements in this area, this series aims to broadcast the views of different bloggers and experts, who share their knowledge and experience on all things related to System Analysis.
It is a well-accepted fact that accurate SI and PI analysis can help identify and resolve critical design issues, prevent costly re-spins, reduce cycle times, and improve product performance. The need of the hour now are integrated analysis tools that visually show you where you might see SI or PI issues on your board, so that you can review and fix them fast.
Cadence® SigrityTM Aurora, our Signal and Power Integrity (SI/PI) analysis solution, is tightly integrated into the Allegro® PCB design environment that provides traditional signal and power integrity (SI / PI) analysis for pre-layout, in-design, and post-layout PCB designs. Sigrity Aurora reads and writes directly to the Allegro PCB database and provides fast and accurate integration of design and analysis results. With Sigrity Aurora, you can visualize the results directly on the design canvas—make changes to the design and see the impact of those changes within the Allegro PCB implementation canvas.
In a recent webinar called, "Signal and Power Integrity Analysis with Sigrity Aurora", we gave a high-level overview of Sigrity Aurora and demonstrated how Sigrity Aurora can help simplify signal and power integrity analysis. Here are some quick highlights from the webinar:
In-Design Analysis is based on SigrityTM Technology and is tightly integrated into Allegro Framework. You can perform in-design impedance, coupling, IR drop, crosstalk, return path, and reflection analysis using the workflows available in the Sigrity Aurora Workflow Manager. With In-Design Analysis, layout designers can find and resolve key signal integrity issues earlier in the design stage without having to learn complex signal-integrity tools. Allegro In-Design (IDA) Environment offers the following workflows:
You can identify and resolve impedance issues in your design by running the impedance analysis workflow. To perform impedance analysis within the PCB layout canvas, select the Impedance Workflow from the Workflow Manager. Then, select the nets to be analyzed using the Select Nets option.
Click Start Analysis to start the simulation. After the simulation run, you need to match the View Mode to the Analysis Mode to view the simulation results.
Impedance results are available in the form of tables, plots, and visions with a color gradient. Select Impedance Vision to overlay the color-coded view of the impedance.
The color-coded scale and the summary table make it simple to find where the signal impedance is high or has jumps or discontinuities requiring a quick design fix. You can save the analysis results and reload them in the future.
When traces run in close proximity to each other, their signals might couple and interfere. You can use the Coupling Workflow to easily filter and select the critical nets in your design to identify where the traces are coupled. A color-coded scale from red to blue quickly highlights any potential problems within the canvas and lists the victim and aggressor nets in a table. Use cross-probing to jump directly to the segments with high coupling, adjust the spacing between the traces, and rerun the analysis to eliminate or minimize the coupling issue.
High speed designs are vulnerable to problems such as reflection and ringing due to signal mismatch. Impedance mismatches, return path gaps, and signal discontinuities are some of the things that contribute to signal mismatch. Therefore, it is important to simulate your design and nip any issues in the bud. Using the Reflection Workflow, you can run simulations using the SigrityTM hybrid solver to find these issues and compare the relative impact of each on signal reflections. You can specify IBIS models for the driver and receiver or use the default models provided. With simulation-driven results on your canvas, it is easy to analyze and resolve signal reflection. Simply select the nets of interest and start your analysis. The analyzed signals are color-coded based on the relative amount of reflection on the signal and you can easily view the details in a table.
Undesired signal noise between the “aggressor” net and a “victim” is one of the major signal integrity (SI) problems in Printed Circuit Board (PCB) designs. With our Crosstalk Workflow PCB designers can run crosstalk simulations using IBIS models directly in the PCB canvas where they can diagnose and quickly fix crosstalk issues. Crosstalk simulations are performed using the Sigrity hybrid solver. You can specify the IBIS models for the driver and receiver or use the default models provided. The simulator looks at all combinations of the victim held low or high, and the aggressor switching towards or away from the victim to identify the worst case. In the results table, each simulated net is listed, with 4 associated numbers for the high state, the low state, the odd mode crosstalk and the even mode crosstalk. By selecting those numbers, you can view the corresponding waveforms. The Crosstalk Visions shows the crosstalk values in the canvas with the color gradient. You can export the results outside the Allegro Layout Editor by exporting them to a spreadsheet.
Managing the signal's return path is crucial to maintaining the signal integrity of designs. A poorly managed return path often degrades the functionality of the circuit. Using the Return Path Workflow, you can quickly determine the quality of a signal’s return path and visualize where the return current is flowing directly on the Allegro canvas. The View Return Path Tables outputs the list of signals with the Quality Factor sorted in descending order. The ideal Quality factor is 1.0, and the greater it is, the less ideal the return path is. For signals with bad Quality Factors, you can start an additional simulation by selecting Run Simulation from the table to visualize the path that the return current is taking. In Return Path Visions, by selecting the appropriate layers for visibility, you can observe the return current density with the color gradient.
The IR Drop Workflow is used to identify potential voltage drop issues in the interconnect that makes up the power delivery network. In the IR Drop Workflow the resistance of PCB traces and planes is calculated by the Sigrity hybrid solver. The IR Drop table displays a list of each current sinking component with PASS or FAIL status, with respect to the Actual Voltage. You can scroll through individual pins and notice the values for Absolute Voltage. While the Actual Voltage for component is measured from an imperfect ground based on the simulation, by selecting the appropriate layers, you can display and review the IR Drop with a color gradient for both, the supply and ground nets.
A new workflow called the Interconnect Model Extraction workflow has been integrated with Sigrity Aurora in the OrCAD® and Allegro® 17.4-2019 QIR4 release to enable greatly simplified and automated interconnect model extraction (IME).
Note: The Interconnect Model Extraction workflow requires a separate license in addition to the base license.
In this workflow, the setup and port generation are done for you. By using the default setting and selecting the nets of interest, extraction becomes a push button. The repeatable process allows you to iterate on design changes quickly and generate repeatable extractions. One such process is virtual prototyping, where you can create mock-up sections of the board and iterate on design changes. This lets you extract the interconnect on each iteration to explore the design space and see what works best from the Signal Integrity perspective. With this push button approach, the time between making changes and verifying the channel work is reduced. You can select whole buses for extraction with either PowerSI or Clarity 3D. You can also view the 3D geometry of the selected nets in 3D Canvas, display the curves for the obtained s-parameters and the model in Cadence® SigrityTM Topology Explorer. When you view the model in TopXP all the signals are represented with their pins.
To obtain more accurate design constraints and reduce design iterations, you can start the analysis earlier in the design cycle using what-if scenarios. Topology Explorer environment allows what-if analysis of signals, power, or both signals and power together. In TopXP you can perform signal and power integrity (SI/PI) analysis using interconnect models that are pre-route (what-if), captured from measurement, or extracted using electromagnetic field (EM) tools such as the Sigrity PowerSI extraction tool Clarity 3D Solver.
TopXP provides an electrical view of the physical interconnect, letting you explore different routing and placement scenarios in the pre-route phase. Within TopXP you can do basic topology extraction with lossless TL models, modify the topology to add blocks, define receivers and transmitters, assign IBIS models, create Spice models, use W-elements for lossy TL, and set up and run simulations and explore waveforms.
It is easy to see how Sigrity Aurora has taken complex signal integrity analysis tasks that typically require specialized tools run by experts and put it in the hands of the PCB designer to resolve issues directly in-design.
This wraps up our summary of the features explored in the webinar. If this piqued your interest in the webinar, you can watch the recording here anytime.
Stay tuned as we explore other highlights from the world of Cadence Sigrity and Systems Analysis. Happy reading!
Signal and Power Integrity Analysis with Sigrity Aurora
IC Packagers: Analyze, Simulate, and Resolve Signal Integrity Issues Using In-Design Analysis Flows
Sigrity Aurora v17.4QIR2 (Online)
For more information on Cadence Sigrity and Systems Analysis products and services, visit www.cadence.com.
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