IC Packaging and SiP Blogs

In today’s ever-shrinking IC Package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to find out the layout mistakes by looking at the changing impedance values and high coupling due to nearby signals. Unfortunately, layout engineers generally do not have exposure to costly and complex signal-integrity tools. Moreover, the time for learning a new and complex tool is a luxury when working with already crunched project deadlines. The good news is that a high-speed analysis and checking environment has been introduced within the Allegro® Package Designer Plus framework. The newly integrated In-Design Impedance and Coupling workflow in Allegro Package Designer Plus SiP Layout Option powered by Sigrity solver allows a quick and easy way to analyze the post-layout package without spending time and effort on a complex tool.

In the 17.4-2019 QIR2 release, a new menu, Workflow Manager, is added to APD Plus with SiP Layout. In this post, we’ll go through the steps for running Impedance and Coupling workflows.

Setting the Package Design for Simulation

Before even starting with the simulation, ensure the following:

• The design must have a ground plane
• The environment variable sigrity_eda_dir points to the latest Sigrity installation. You can access this variable from Setup ─ User Preferences ─ Paths ─ Signoise

Impedance Analysis Workflow

True impedance issues in a design can be identified and resolved by running the impedance analysis workflow. To open the Analysis Workflows interface, choose Analyze ─ Workflow Manager.

Use the Select Nets option to select critical nets from the design. These nets get listed in the Selected (X)Nets section of the UI. If you enable the Apply Selection to All Workflows checkbox, the selected nets are also used for the coupling workflow.

Click Start Analysis to start the simulation. If you see the following failure message, it means the sigrity_eda_dir variable is not set. Open User Preferences Editor and set the variable correctly and run the simulation again. Setting up and running the simulation is quite easy and can be done very quickly.

Not seeing this message indicates a successful run and results are loaded in the workflow. Impedance analysis ignores the wire bonds present in the design while simulating. Now, select Impedance Vision to overlay the color-coded view of the impedance results on the design canvas. The color-coded scale from red to blue, along with the summary table, makes it simple to find where the signal impedance is quite high and requires a quick design fix. A high impedance can be caused by various reasons, such as gaps in the ground plane, layer changes, or changes in trace width; but, one thing is for sure - high impedance needs a quick design fix. To minimize the impedance, click on the data point in the table to navigate to the trace. Fix the issue and rerun the simulation to verify it.

Save the analysis results, and reload them in the future. You can also save the complete workflow selection and settings using the Save Workflow option and then reuse the saved workflow by importing it using Load workflow.

Coupling Analysis Workflow

Potential coupling issues can also be found while you are finalizing your design by running the coupling analysis. Select Coupling Workflow from the pull-down menu in the Analysis Workflows UI.

Run the simulation as mentioned in the impedance analysis flow. Select Coupling Vision after the simulation is completed and analyze the results in the canvas. Traces with coupling issues are highlighted in the canvas and are listed in the table as victim and aggressor nets. Adjust the spacing between the traces to eliminate or minimize the coupling issue. Run the analysis again to check your corrections.   

Summing Up

In-design Analysis in package design helps layout designers to find and resolve the key signal integrity issues without learning the complex signal-integrity tools.

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