ASCENT: Some Basic Rules for Design Verification

In part 1 of this blog post, we covered the model-less aspect of Allegro^® System Capture’s Design Integrity solution and now here we are with part 2.

So, maybe scrolling through or navigating 200-300 pages of a design to catch logic design errors isn’t the same as watching paint dry, but let’s face it, does anyone really want to stare at a screen for hours on end? And yes, sure, you can use simulation analysis results but these may not catch all the errors in a design.

If you are an Allegro System Capture user, why not rely on the 40 odd basic rules available, by default, to check the design for you? Here are some rules to get you started:

• Differential Pair Net Polarity Mismatch - Say you have a positive member of a diffpair signal connected to a negative pin of an IC, this rule will report it. You can define the patterns for nets/pins with positive and negative polarity in the Parameters tab of the Schematic Audit Settings dialog.
• Connected IC NC Pins – Design Integrity reports IC NC pins that are connected. Yes, I guess you didn’t actually mean to connect them, but a colleague stopped by to chat and you got distracted. Of course, that was in the pre-COVID era when we had 3D colleagues, not 2D.
  Design Integrity detects NC pins on the basis of the IC pin names starting with NC but not followed by a letter.
• Single-Connection Nets - Nets connected only at one end are reported as single-connected floating nets. Note that NC and interface nets are excluded from this rule.
• IC Input Pins Without Driver - After checking all the topologies connected to an IC input pin, this rule checks whether drivers are pulled up or pulled down through resistors, and reports IC input pins with nets that have no driving source.
• IC Power and Ground Pins Without Voltage - Power/ground nets and nets connected to power/ground pins are checked for any voltage values and nets with no voltage values are flagged. Design Integrity excludes signal nets connected to power/ground pins of ICs.   
• Low/High Pull-up Resistance Value and Low/High Pulldown Resistance Value - Reports pulldown resistors with lower or higher resistance values than the configured min or max values. And the values are in your control. Define them in the Parameters tab of the Schematic Audit Settings dialog.

 
What’s more, you not only control which rules to check, but also how rule violations are reported. Define whether a rule is reported as an error, warning, or information, or choose not to have the error reported at all! It’s up to you. Also, filter for specific rules to make them easier to find. If you are a site admin, you can also control the default rules that can be run at various violation levels, such as error, warning, info by manually modifying the site.cpm file.

Once a violation is found, it’s so easy to find it on the design canvas. Select the violation and the exact location is displayed on the canvas.

So, go on, start exploring all the rules available to you!

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