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Featured

DesignCon 2025 Highlights and Papers on Demand

The Cadence MSA team had a GREAT DesignCon highlighting how Cadence can help you…

MSATeam
• 2 min read
featured , DesignCon , Advanced IC packaging , PCB design

Designing High-Performance Sensor Packages to Ensure Optimized Performance

In an era where technology and connectivity reign supreme, electronic, and mechanical…

Vinod Khera
• 4 min read
featured , IC Packaging , Allegro X Design Platform , EDA , MCAD-ECAD

Machine Learning Is Revolutionizing IBIS-AMI Optimization in High-Speed Design

The complexity of IBIS-AMI models used in simulating serial links has increased to…

MSATeam
• 1 min read
featured
System, PCB, & Package Design 

Latest blogs

DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 2 of 2)

In part 1 of this two-part blog post, we analyzed how you can define a parts lifecycle…

• 1 min read
Library and design data management , EDM , PCB design

IC Packagers: The Spaces Between Your Dies

Die stacks are starting to look more like skyscrapers every year. If your packages…

• 4 min read
IC Packaging , APD , SiP Layout

BoardSurfers - Aerials and Bails: Take a Walk on the Wild Side...with Auto-Roami…

We have had this question before, so it’s a good one to remind everyone of in case…

• 2 min read
APD , PCB Editor , SiP Layout

IC Packagers: Constructing Components from Manufacturing Data

We’ve all been there. The only (or most accurate) data that we have for a component…

• 5 min read
IC Packaging and SiP , APD , SiP Layout

BoardSurfers - Aerials and Bails: How to Split a Viastack

Today’s compact and powerful devices require small and high-density PCBs. Tight routing…

• 2 min read
APD , PCB Editor , SiP Layout , Allegro

DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 1 of 2)

This is the first of a two-part blog post on managing part obsolescence using Allegro…

• 3 min read
allegro edm , Library and design data management , EDM , PCB design

IC Packagers: A Classic Revisited - Ball Map Spreadsheets

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google,…

• 4 min read
APD , SiP Layout

BoardSurfers: Text Labels and Film Views Help Intelligent Designers

Last time, I talked about color and visibility as it relates to simplifying your…

• 5 min read
APD , Allegro Package Designer , Allegro PCB Editor , SiP Layout

IC Packagers: The (Copper) Pillars of Modern Design

Wire bonding has been around forever. Flip-chip mounting? That’s been around for…

• 7 min read
IC Packaging , IC Packaging and SiP , SiP Layout

BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to…

• 4 min read
APD , PCB Editor , PCB design , SiP Layout

IC Packagers: Dealing with Large Forms in Low Resolution Screens

Our packages and boards are becoming complex and so are the design tasks we perform…

• less than a min read
IC Packaging and SiP , Allegro Package Designer

IC Packagers: When Being Two-Sided is a Good Thing

With each new generation, demand for smaller, faster, lighter, more efficient is…

• 5 min read
IC Packaging & SiP design , SiP Layout

BoardSurfers - Aerials and Bails: Minimum Screen Resolutions and Large Forms

The Cadence® Allegro® backend layout tools are large, complex, highly-capable environments…

• 5 min read
PCB Editor , Allegro Package Designer , PCB design , SiP Layout

How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

With the buildout of 5G wireless networks and the constant demand for bandwidth in…

• 1 min read
Serial link analysis , ami builder , equalization , PAM-4 , IBIS-AMI , DesignCon 2019 , SerDes , Sigrity , SystemSI

IC Packagers: Expanding Your (Thermal) Repertoire

The process of attaching a component to your package substrate involves many factors…

• 4 min read
APD , CTE , Allegro Package Designer , SiP Layout

IC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout

How do you go about testing your IC or package substrate when it comes to physical…

• 4 min read

Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

As transistor device scaling gets closer and closer to physical limits, more and…

• 2 min read
advance packaging , Silicon-interposer 2.5D package-based test , reference flow , Samsung , CDNLive 2019 , package design , DesignCon 2019 , FO-PLP , Sigrity , CDNLive San Jose , Package signoff , Advanced Package design and sign-off reference flow

BoardSurfers: Make Menus Your Own – Customizing Menus and Toolbars with Things You…

Flexibility and the ability to customize the software/environment to your own personal…

• 7 min read
Allegro PCB Editor , SiP Layout , SKILL

IC Packagers: Coming Soon to a Blog Near You…

What is new in the Cadence® SiP Layout and APD tools? Is there reason to get excited…

• 1 min read
Digital SiP design , IC Packaging & SiP design , Allegro Package Designer , SiP Layout

How to Accelerate Your Thermal Aware PI Design?

In modern electronic systems, there may be tens to hundreds of DC rail voltages used…

• 2 min read
PCB , DC , PI , DesignCon , PDN , Power Integrity , OptimizePI , DesignCon 2019 , PowerTree , electrical-thermal co-simulation , Sigrity , thermal , PowerDC

BoardSurfers - Aerials and Bails: How to Hide the Design Path in Art File

Before manufacturing, PCB fabricators analyze Gerber data to verify if it is manufacturable…

• 1 min read
Gerber , Manufacture , artwork , environment variable , Allegro PCB Editor

BoardSurfers: Place Replicate to Increase IP Reuse and Decrease Design Time

Once you have successfully designed and optimized an area of your substrate today…

• 4 min read
Place Replicate Module , Allegro PCB Editor

Power Plane Loop Inductance Guidance for PDN Designers

Gaining an understanding of power plane loop inductance is important for efficient…

• 1 min read
SI , DesignCon , PDN , Power plane loop inductance , DesignCon 2019 , Signal Integrity , Sigrity , PowerSI

BoardSurfers: Validating Your Shapes

Your design is near completion. Except that you’ve got an area of your plane shape…

• 5 min read
PCB Editor , PCB design and layout , Shape Checks , Allegro

BoardSurfers: Dynamic Shape Voiding – Getting the Most Out of the Tool

Dynamic shapes; whether used on a negative or positive artwork layer, for power,…

• 7 min read
Constraint Manager , PCB design , Allegro PCB Editor

Join us at CDNLive Silicon Valley 2019

Cadence will kick off this year’s CDNLive worldwide user conference series starting…

• 1 min read
CDNLive , CDNLive 2019 , CDNLive San Jose

Exposing Adaptive EQ in 32 Gbps Receivers

It is no secret that serial link data rates have skyrocketed over the past 15 years…

• 1 min read
dfe , SI , FFE , DesignCon , Adaptive Equalization , AGC , IBIS-AMI , EQ , DesignCon 2019 , Signal Integrity , SerDes , Sigrity , SystemSI , Automatic Gain Control

BoardSurfers: Allegro 3D Canvas—Visualize the Board as You Design

Today’s dense and complex PCB designs require realistic 3D view to investigate the…

• 3 min read
PCB , Layout , 3D , PCB design , Allegro PCB Editor
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