IC Packaging and SiP Blogs

This marks our third and final look at the biggest new features in this major update. We’ve already looked at features spanning from performance gains to improvements in the graphical canvas in the first and second installments in this series. Updates to the base product and items for the advanced Silicon Layout option nodes  - there’s something for everyone.

Keeping with that sweeping scope of improvements, let’s look at our final set of updates in Allegro^® Package Designer Plus, which focuses on routing and power delivery solutions coupled with a feature you can use if you have highly specific mask organization requirements for your GDS manufacturing outputs.

New Types of Routing and Shielding Structures 

If you haven’t tried the new Create Structures command (Found under Route – Unsupported Prototypes), you’re missing out. One of the greatest things here is the ability to rapidly create parametric structures for differential pair transitions. Not only can you define the entry and exit strategies to the vias, as shown here:

But you also have access to many different shape styles for the keepouts that surround and shield your differential pair nets:

These structures can be placed on the same layer as the routing or on adjacent layers, offering protection from surrounding signals and noisy power planes.

The advantage of parameterizing these elements is the tight tie-in with your constraints, feedback from your signal integrity experts, and the reduced complexity normally found in attempting to manually draw more complex boundaries.

While this command is listed under the Unsupported Prototypes category, this is largely because we are seeking feedback from you, our user community, to help us expand the options to cover all the parameters that you need to adjust when defining these structures. Is there a style of keepout you use but isn’t listed? Do you find yourself coming back in ECOs and needing to tweak parameters for all the instances of your existing structures? Help us to understand how you will apply these structures so our team can round out the functionality set!

Power Plane Generation from Pin/Via Patterns

Continuing with some of the prototype-level features, let’s look at the creation of your power delivery solution. These get more complicated with every new design, it seems. Most designs today have a more involved power structure than a single power ring and ground flag supporting a wire bond die.

Enter the SI Layout Power/Ground Plane Generator, the UI for which appears below. You will need to be sure to enable this command with the package_plane_gen_beta user preference. With this tool, you build your plane areas based on where the pins that reference them exist in your layout. Rather than define the areas manually by highlighting your power nets in the layout then looking for clusters, allow the tool to perform this on your behalf.

Options range from a flood net to cover the layer where no other plane is poured to regions defined by a bounding shape (convex hull) surrounding pin groups to rectangular regions like blocks around regular clusters of pins that identify power domains inside of the chip.

Unlike many power delivery solutions, this tool allows you to come back to saved parameters and tweak, refine, and update as your design progresses; then regenerate all the planes at the push of a button.

Should you want to lock down specific areas to prevent future parameter changes from affecting that perfect region, save the shapes and they will be locked in the design, safe from any changes as you work on other areas in the design.

Rather than spoil the surprise of the complexity of plane areas the tool can generate with a picture, I encourage you to try the tool out for yourself. Generating all the planes for a layer or the entire design takes mere seconds. Have some fun! You may find relationships and groupings of pins that you didn’t spot from a wide zoom view of your design!

Stream Out Functional Updates

GDS is more than just a manufacturing output. It is an interface to the Cadence formal sign-off platform, Pegasus Verification System, for language-based design rule checking. The output can feed into many analysis tools with the proper text labels on the pins and other key features of the layout. In a pinch, the format even serves to share design intent with your IC design team.

However, some of these flows require a greater granularity than just a straight mapping from your Allegro Package Designer Plus class and subclass (CONDUCTOR/TOP, for instance) to a GDS layer + data type pairing. If you need your metal fill for density balancing on a unique entry inside of the GDS so that it can be considered for density checks but ignored for LVS considerations, how do you best accomplish this?

Allegro Package Designer Plus makes this easy for you. The layer mapping conversion file editor, shown in the next image, provides you with the basic breakdowns that are most common. For sending data to manufacturing, where the layer represents ALL the geometries to be part of the mask, this interface should provide everything you need.

To split different parts of your shapes – maybe the metal fill mentioned above, or even the degassing holes – to a different GDS mapping, you need to go a bit further. This is not part of the conversion file editor above to hide the daunting level of configuration options you can find.

However, do you wish to access these advanced mapping options, to bring up the conversion file in any text editor of your choice? There, you can refine the mapping entries even further. An example would be:

The top is a mapping created through the conversion file GUI. Below, all the metal on the TOP layer is mapped to 2/1 EXCEPT the dummy metal fill. This goes to the 2/2 mapping, instead. For sending data to Pegasus Verification System or PVS, this allows you to easily differentiate the use of the geometries on a layer to exactly match the sign-off rule deck provided by your manufacturing partner.

The complete list of restrictions is available through the documentation, of course. Metal fill and degassing holes are the most common I get questions about, however. If this is something you’ve had questions about in the past, reach out to our team of customer support experts for assistance. They’ll be able to set your feet on the path to success in no time!

Download the Latest HofFix Now and Try the Latest Updates Out!

Hopefully, over the last three weeks, we’ve whetted your appetite for the updates to be found in the Allegro Package Designer Plus product. If so, download the latest 17.4-2019 Hotfix 019 and try it out for yourself. There’s no substitute for experiencing things for yourself!

Do SUBSCRIBE to be updated about upcoming blogs. If you have any topic you want us to cover first or any feedback, you can write to us at pcbbloggers@cadence.com.