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Tyler
Tyler
24 Jun 2020
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IC Packagers: How to Fix Padstacks that Aren’t Showing All Their Layers

IC Packagers: Cadence Allegro BlogWe talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up.

Not all your components are dies (obviously!), and certainly are not all flip-chip, wire-bond, or BGA style mounting. There are resistors, capacitors, inductors, and endless other objects. In many cases, these ARE properly represented through pin padstacks.

But, if you initially brought these components in as the wrong component class, identifying them as die components, you probably noticed that the pin’s layer span is locked at a single layer SMD style pad. That’s correct for dies, as we discussed, but how do you fix components where this is NOT an accurate representation of the part?

Correcting Component Types 

First things first: don’t panic! This is a common mistake. Many components brought in from the front-end schematic, if you didn’t configure the component class, will default to class IC (a die); these are, after all, the prevalent component types in your package designs. Allegro Package Designer, just like the Allegro PCB layout tools, is perfectly suited to handle these. 

Make sure all your components are accurately identified in the design. Doing so will allow the tool to take care of, even validate, aspects of the substrate for you automatically. It will guide which pins need (or even allow) bond wires and which need to be checked for tombstone assembly issues. The primary BGA component – not including any package-on-package or other internal package elements – is the only one that is used to generate the final board level component for mounting on the next substrate.

There are two main ways to fix component class assignments to object. First, there is a package integrity check (Tools – Package Design Integrity…) which will search for these and, optionally, correct them. This is the quickest mechanism. However, it may not assign the component class you want. Hence, I recommend you run in check only mode – leave the Fix errors automatically option disabled first. Check the results. If you agree with all the component class recommendations, re-run the tool a second time with the fix option on.

If you do not agree with the recommendations, or you want complete control over the class assignments, use the Logic – Edit Parts List.. command, instead. Here, you can pick each of the components and manually change the class assignment to the intended one.

Of course, you can correct the component classes in your front-end design as well, then push those changes into the layout. If you’re using a schematic, this is the ideal solution. Still, it doesn’t address the issue we opened the conversation with.

Removing Pad Layer Span Restrictions

Upon correcting the component types, you can then address the padstack layer spans using the Tools – Package Design Integrity toolbox. Here, look under the General category for the Non-Die Pad References check. Shown below, the check will remove these pad references for non-die components and restores the full span of the pads and the drill information.  

This can help you fix designs where you’ve made a mistake. But, use with care. Tools found in the integrity check command indicate and resolve common design errors. If you can avoid these situations in the first place, you will doubtless save yourself time – and aggravation – building your next package!

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