System Design and Verification Blogs

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we collaborated to develop and validate our solutions with their IP. Then with the top customers in the world, who must continually overcome increasing SoC complexity due to architecture changes such as cache coherency, increased IP integration, and the massive traffic demands to come from those interfaces and memories. We created the Cadence Interconnect Workbench to increase productivity and manage the exploding performance data, and have now expanded to include support for AMBA5.

Nick Heaton describes performance analysis for an Arm-based Server SoC in his blog, Cycle-accurate Performance Analysis now available for latest AMBA5. He will be attending Arm Techcon to present more details on this project and is available to meet with customers who want to discuss these details further.

The most important thing to understand about the Interconnect Workbench is its value in properly configuring the Arm interconnect IP for your SoC application. While this includes functional verification, it’s not about finding functional bugs in the IP. Interconnect Workbench helps find bugs in address mapping, correctly connecting cascaded or heterogeneous interconnect fabric and other configuration errors. These configuration options also impact performance, and thus performance analysis is an invaluable capability. The ability to automatically generate a testbench for new interconnect configurations speeds the validation process, enabling a “what-if” approach to SoC architecture and interconnect design.

There are three use modes of the Interconnect Workbench, as shown in Figure 2. The first is characterizing the performance of your configured interconnect, using Interconnect Workbench with the Xcelium Parallel Logic Simulator. What is the maximum throughput for each master-slave path? The second use mode is to assess system load use cases, by applying specific multi-master traffic scenarios. These can be used to stress the interconnect to look for outliers in handling overload conditions. The third use mode is to measure the system under software traffic with all IP integrated into the SoC. This is where Interconnect Workbench on Palladium becomes crucial, for the capacity and system throughput executing the software. Read more about that here.

The collaboration with Arm has spanned these years and can be measured by all the interconnect IP that can be analyzed with the Interconnect Workbench:

• Corelink Coherent Mesh Network Family
  
  • CMN-600

• CoreLink Cache Coherent Network Family
  • CCN-512
  • CCN-508
  • CCN-504
  • CCN-502
• CoreLink Cache Coherent Interconnect Family
  • CCI-550
  • CCI-500
  • CCI-400
• CoreLink Network Interconnect Family
  • NIC-450
  • NIC-400

And Arm and Cadence have produced a host of joint marketing collateral to help customers with adoption and improving their productivity building Arm-based SoCs.

• White paper
• One of many joint presentations at Arm Techcon
• Better PPA with Arm Corelink System IP video

We look forward to many other phases of our collaboration, solving the latest SoC and System Enablement challenges when developing Arm-based SoCs.