How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 differs from traditional NRZ signaling in that it transmits 2 bits per symbol, effectively reducing the need for bandwidth by half.

Figure1. PAM4: 4-level pulse amplitude modeulation.

To enter this hot and competitive market, Cadence purchased a startup company in late 2017 called “nusemi Inc.”, and immediately began work on a 112Gbps PAM4 SerDes IP offering.

At DesignCon 2018 that January, nusemi engineers initially sat down with Product Engineering and R&D folks from the SystemSI product line to figure out how to produce IBIS-AMI models for their advanced SerDes , that could be distributed to customers. Kumar Keshavan from the SystemSI R&D team went to work immediately to understand the advanced algorithms in nusemi’s “Magpie” SerDes IP and to put the necessary infrastructure and building blocks in place to enable SystemSI’s AMI Builder technology to produce the model. There were numerous challenges, including the handling of PAM4 equalization, modeling new clock and data recovery (CDR) algorithms, incorporating feed forward equalization (FFE), and handling Gray coding, but these were overcome. Exactly one year later, the nusemi and SystemSI teams delivered a joint presentation at DesignCon (DesignCon 2019) describing these technical challenges, showing initial model-to-hardware correlation between the Magpie first silicon test chip and SystemSI simulations, using that newly-developed IBIS-AMI model.

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How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

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