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Gaining an understanding of power plane loop inductance is important for efficient printed circuit board (PCB) designs. Unfortunately, board designers too often use inappropriate rules of thumb when laying out the power delivery network (PDN) of complex designs and end up making costly board re-spins to find and resolve power plane loop inductance problems. Power plane loop inductance is a critical PCB artifact that impacts PDN frequency response and noise coupling, but most PCB designers do not have time to simulate the impact of different design considerations on power plane loop inductance before tape out.
At DesignCon 2019, engineers from Oracle and Samtec teamed up with Cadence to simulate power plane loop inductance using Cadence PowerSI and correlate these results with measurements on three very different hardware design. Using the simulation validation from these three cases, we took a simplified power plane design on a PCB and varied several key design parameters to show their impact on power plane loop inductance in simulation. Reviewing these results, designers and engineers will get a better understanding how various design parameters can impact power plane loop inductance.
To further demonstrate the real-world impact of power plane loop inductance, we simulated a large Oracle motherboard that required two re-spins to resolve a problem with noise coupling from a power plane onto nearby PCIe lanes. We showed that our Cadence PowerSI simulations predicted the reduction in the aggressor’s loop inductance from the first to the last version of the board, leading to a final design that met PCIe compliance.
Check out our joint DesignCon paper below to get a better understanding of how common layout design parameters affect power plane loop inductance.