Signal and Power Integrity (PCB/IC Packaging) Blogs

The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads.

SIGRITY2019 HF1

For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the Sigrity 2019 HF1 production release, see the README.txt file.

At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com, click the LINUX or WINDOWS tab, and select the SIGRITY2019 release name to access the related files.

Here is a list of some of the important updates in the Sigrity 2019 HF1 production release:

• Clarity 3D Solver
  • Native Window Support Added: The Clarity 3D solver has been enhanced such that now you no longer require a Hyper-V machine to run Clarity simulations on a single Windows machine.
  • Anisotropic Dielectric Material Support Added: Two new options, Isotropic and Anisotropic, have been added in the Dielectric tab of the Material Manager form in Clarity 3D Layout and Clarity 3D Workbench that enable you to specify the dielectric materials as isotropic or anisotropic.
  • Support Added to Automatically Calculate the Maximum Length of a Signal Net: In this release, if you specify -1 in the Signal Net Max Edge Length field and select the Local Map option, Clarity 3D Layout and Clarity 3D Workbench automatically calculate the maximum edge length for signal nets during mesh generation.
  • Port Wizard Enhanced in Clarity 3D Layout: You can now use the Port Wizard in Clarity 3D Workbench to create ports for discrete components, such as resistors, inductors, and capacitors.
  • Support for SPICE Models using Broadband SPICE Added in Clarity 3D Layout: A new option, Generate SPICE model by BBS, has been added in the workflow pane that enables you to automatically convert the network parameter results for the current simulation to a SPICE blackbox model.
  • Support Added for Cut-Stitch Flow: Support for cut and stitch flow has been added in Clarity 3D Layout. The cut and stitch flow speeds up the simulation by splitting one project into several sub designs and solving them individually.

For detailed information, refer to the Clarity 3D Layout User Guide and Clarity 3D Workbench User Guide on Cadence Support portal.

• Celsius Thermal Solver
  • Expanded Electrical-thermal Analysis Capability to Heterogenous Packaging and 3D-IC Designs: After integration with Voltus (Chip Power Sign-off Tool), the Celsius Electrical-thermal analysis capability has now been extended to allow integrated 3D-IC, TSV, and PKG designs. 
  • Enhanced Transient Thermal Analysis of IC Designs Including Multiple Power Modes within the Chip: The transient thermal analysis capability of Celsius has been enhanced to allow multiple power modes within the chip.
  • Implemented JEDEC Standard Environments for Thermal Characterization of Packages with PCBs: Celsius allows the use of JEDEC standard specifications as templates for test-board design and analysis. This ensures standardized thermal analysis and measurements for consistency.
  • Implemented Component Thermal Models for Electronic Packages: Using Celsius, you can now create generic component thermal models that are commonly used in the electronic packaging industry. Celsius supports the following thermal models: Two Resistor Model, Delphi Model, and Voltus Thermal Model.

For detailed information, refer to the Celsius Thermal Solver User Guide on Cadence Support portal.

• Gds2Spd Translator Enhanced

You can now perform GDS to SPD translation without importing a .map, .layermap or .tech file in Gds2Spd Translator. The translator also lets you specify the design type for translation, set up layers and labels for translation, perform automatic clustering of vias, and translate dielectric layers as metal layers.

For detailed information, refer to the Translators User Guide on Cadence Support portal.

• Sigrity Executables No Longer Available in Allegro Installation

This is an early notification for the users who use Sigrity Aurora, Allegro^® IDA, Topology Explorer, or SystemSI products. Starting from the Allegro 17.4-2019 QIR1 release, to be able to use these products, you will have to install the following two releases:

• Sigrity 2019 HF1 or a later version
• OrCAD^® and Allegro^® 17.4-2019 QIR1 or a later version

On Windows, when you install Sigrity 2019 HF1 or a later version, the installer will automatically set the SIGRITY_EDA_DIR environment variable to point from the SPB installation to the Sigrity installation directory. However, in Linux, you will need to manually set this environment variable after installing Sigrity 2019 HF1 or later version. This setting can also be specified in the Allegro environment file.

For more details about these and all the other new and enhanced features introduced in this release, see What's New in Sigrity 2019 HF1.

Please send questions and feedback to sigrity_rmt@cadence.com.

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Sigrity Release Team