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  • Discussion

    bias point blowup in pspice 9.1 (demo) Locked

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    Latest over 16 years ago
    by ke0ff
  • Discussion

    PCB Editor 16.2 - How to start the VIA ARRAY GENERATOR Locked

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    9 replies
    Latest over 16 years ago
    by Alexandra
  • Discussion

    Concurrent Design in CIS Locked

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    5 replies
    Latest over 16 years ago
    by dschaefer
  • Discussion

    How can I make Macros Locked

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    Latest over 16 years ago
    by Ejlersen
  • Discussion

    How to change the rats' (net connection wire) color in Allegro PCB Editor Locked

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    6 replies
    Latest over 16 years ago
    by Ejlersen
  • Discussion

    Exporting/saving footprints from brd file Locked

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    Latest over 16 years ago
    by archive
  • Discussion

    problem with importing design into Cam 350 Locked

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    Latest over 16 years ago
    by joebrewer109
  • Discussion

    How to copy in PCB Editor the board outline on the bottom layer as dynamic shape. Locked

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    2 replies
    Latest over 16 years ago
    by Alexandra
  • Discussion

    dbGet and playing with the database Locked

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    6 replies
    Latest over 16 years ago
    by BobD
  • Discussion

    Viewing OVM Transactions in Simvision Locked

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    6 replies
    Latest over 16 years ago
    by StephenH
  • Discussion

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    3 replies
    Latest over 16 years ago
    by pcbgeorge
  • Discussion

    CIS question text justification Locked

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    2 replies
    Latest over 16 years ago
    by Psycho Pete
  • Discussion

    Tear drop in allegro15.7 Locked

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    3 replies
    Latest over 16 years ago
    by CubbyBear
  • Discussion

    accessing/quering value of simple_port using Reflection API Locked

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    1 reply
    Latest over 16 years ago
    by hannes
  • Discussion

    How to delete unconnected pins? Locked

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    2 replies
    Latest over 16 years ago
    by Prasanna
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