Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hi, I want to route my design in SoC Encounter and I use the follow script for Nanoroute:setNanoRouteMode -quiet routeFixPrewire truesetNanoRouteMode -quiet route_selected_net_only falsesetNanoRouteMode -quiet routeWithTimingDriven falsesetNanoRouteMode -quiet routeTdrEffort 1setNanoRouteMode -quiet drouteFixAntenna truesetNanoRouteMode -quiet routeWithSiDriven truesetNanoRouteMode -quiet routeSiLengthLimit 200setNanoRouteMode -quiet routeSiEffort normalglobalDetailRouteThis work without problem. But as I want to avoid routing on the first layer, I also add the follow option:setNanoRouteMode -quiet routeBottomRoutingLayer 2But with this option the program report an segmentation fault.What's I'm doing wrong?Christian
Dear Christian, Its not a bad idea to block M2 ( metal 2 layer ) on your design ,But one thing is it really possible to block whole M2 in the design think practically . NOhow ever you can do the same by blocking M1 in your design , as STD cell pins can reach M2.Suggestion . 1. Add M2 routing blockage over a region to restrict so .2. check placement ( and see unplaced count is = 0 ) If you are blocking M2 for only clock nets then its OK then use setAttribute -net @CLOCK -bottom_preferred_routing_layer 2 -top_preferred_routing_layer 4setNanoRouteMode routeTopRoutingLayer 4setNanoRouteMode routeBottomRoutingLayer 2
Thank you for your answer, but I think there is a misunderstood.What I want is to route on layer 2-7 compared to the "normal" 1-7, so it is the first layer that I don't want to route on.The real problem is that the command routeBottomRoutingLayer give me a segmentation fault.Is there an incompatibility of this command with others Nanoroute options?Thanks againChristian
Hi Christian,As Mohanch mentioned, it is impossible to route layer 1-7 if you have pin on metal1 (note: layer1 is metal1 and layer 7 is metal7).Most std cell pins are on metal1.Regards,Eng Han
Hi Christian,As Mohanch mentioned, it is impossible to route layer 1-7 if you have pin on metal1 (note: layer1 is metal1 and layer 7 is metal7).Most std cell pins are on metal1.If you ready want to route 2-7, then you must also tell the software which net you want to route. You have to make sure those net does not need to connect to metal1 pin.Regards,Eng Han
HI , Since 3 years we are using Soce and i have not fased such problems ,Its duffecult to justify the right reason for such issues spacific to your design .check how are the WARNINGS and ERROR msg. at the time of loading and running nano route.In practical I have even limited using some layers on all subversion of 4.1 . -NO PROBLEM .If possible can you please let me know on which technology and your encounter.log & cmd file ... not all only the Nano route attrebuts and reported log. advice before sending more details 1. before globaldetail route just check Global Route .and check each layer conjesion map . during Global route check :
#Start data preparation...
# #Using automatically generated gcell grid.
# Layer Direction #Track Blocked #Gcell Blocked
# Metal 1 V 10249 37.73% 466489 26.39%
# Metal 2 H 10250 15.61% 466489 28.03%
# Metal 3 V 10249 12.81% 466489 30.53%
# Metal 4 H 10250 30.34% 466489 26.46%
# Metal 5 V 8200 29.28% 466489 25.71%
# Metal 6 H 3416 27.51% 466489 26.03%
# Metal 7 V 1282 8.27% 466489 18.09%
# Total 53896 27.36% 3265423 24.46%
#cpu time = 00:00:09, elapsed time = 00:00:19, memory = 200.00 (Mb)
#start global routing iteration 1...
#cpu time = 00:00:03, elapsed time = 00:00:07, memory = 202.00 (Mb)
#start global routing iteration 2...
. . .
#start global routing iteration 6...
#cpu time = 00:00:14, elapsed time = 00:00:25, memory = 202.00 (Mb)
# Layer #OverCon %OverCon
# Metal 1 2 0.00%
# Metal 2 0 0.00%
# Metal 3 2 0.00%
# Metal 4 0 0.00%
# Metal 5 0 0.00%
# Metal 6 0 0.00%
# Metal 7 0 0.00%
# Total 4 0.00%
#Complete Global Routing.
#Total wire length = 580805 um.
#Total half perimeter of net bounding box = 227492 um.
#Total wire length on LAYER M1 = 88617 um.
#Total wire length on LAYER M2 = 294704 um.
#Total wire length on LAYER M3 = 221670 um.
#Total wire length on LAYER M4 = 5812 um.
#Total wire length on LAYER M5 = 5344 um.
HI , Since 3 years we are using Soce and i have not faced such problems ,Its difficult to justify the right reason for such issues specific to your design .check how are the WARNINGS and ERROR msg. at the time of loading and running nanoroute.In practical I have even limited using some layers on all subversion of 4.1 . -NO PROBLEM .If possible can you please let me know on which technology and your encounter.log & cmd file ... not all only the Nanoroute attributes and reported log. advice before sending more details 1. before globaldetail route just check Global Route .and check each layer congestion map . during Global route check :