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I have access to the IBM PDKs for both 65nm (cmos10lpe) and 45nm (soi120S). I wanted to test the PDK and the DRC tool so I made a layout containing just one nmos and ran DRC on it. To my surprise, I got DRC errors for the IBM PDK nmos cell using the IBM PDK DRC runset. Shouldn't the cell provided in the PDK be error-free?
Another question is specific to the 45nm PDK (soi120S): on the nmos and pmos cell, there are poly layer strips (pc) that are close but separated from source and drain. What purpose do these poly layer strips serve?
Finally, I am quite new to layout design with PDKs. In fact, I have only used Cadence gpdk and TSMC 0.25um PDK before; both are much easier to use than the IBM 65nm and 45nm PDK that I have to use for my project. Does anyone know if there is a good layout tutorial that uses IBM PDKs, or if anyone is expert with these PDKs, may I ask you more related question privately?
Thanks anyone for their help in advance!!
I don't know anything about specific PDKs, but if you run DRC on just one cell, you're bound to get errors relating to the fact that it's just one cell and not part of a chip. You may have to turn off options in your DRC deck for verifying single cells.