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Currently I am working on the physical implementation of a simple
mixed-signal design. The problem is that all testcases for functional
verification were written only for the digital block (I/O and analog
blocks were not considered). Therefore I need to generate the verilog
and SDF files only for the digital block. How to do this in FE (version
For the verilog file, I tried the command "saveNetlist -module xyz.v" but this not work recursively into the submodules.
I tried also to generate the SPEF files for the digital block and so
use the ETS to generate the SDF files, but it seems FE is not able to
generate a parasitics file for an instance/module.
Can anyone help me?
When you floor-plan the chip in FE, Is it possible to use "partition" to isolate your digital block from the others?, if so, you get a work-around for the issue: you can place&route the digital partition first (separately), create .v and spef file for the partition and get time closure, then, push it back into top (chip) level and finish chip route. I did this way for a mixed-signal block and FE worked pretty well for me. Tongju
Hello Tongju,As the physical implementation was done I preferred to write out set_load and set_resistance files (rcout -setload xyz.load -setres xyz.res) and edit them by hand to point directly to the target module. So I generated the SDF files using ETS and it seems they are ok.In the next designs I will follow your suggestion. Thanks for your help.Regards,Cristiano.