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I compiled very simple SystemVerilog file including VMM library with ncverilog just using +sv option
I found much error message in "vmm.sv" file and don't know what that means
I will show some part of the ncverilog log file below.
ncverilog(64): 06.20-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.TOOL: ncverilog(64) 06.20-s005: Started on Mar 12, 2009 at 18:36:11 KSTncverilog +access+rwc +incdir+/user/Galguzima/test/vmm-1.0.1/sv +sv simple_test.svfile: simple_test.sv const ref logic [7:0] unpack[); |ncvlog: *E,FNDKWD (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|28): A SystemVerilog keyword was found where an identifier was expected.(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2) const ref logic [7:0] unpack[); |ncvlog: *E,ILLPDL (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|38): Mixing of ansi & non-ansi style port declaration is not legal.(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2) const ref logic [7:0] unpack[); |ncvlog: *E,EXPSMC (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|54): expecting a semicolon (';') [3.2.2(IEEE)].(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2) endfunction
You should be using version 8.2 of IUS if you want to use SystemVerilog. Older versions work, but 8.2 has the broadest language support compared to 6.2 or 8.1. Unfortunately I can't recall what limitations there were in 6.2, but from the message it looks like the compiler wasn't expecting to see the "const" keyword and has confused it with a variable name.
Can you try again in 8.2?
If you'd like some help with porting your code to IUS, send me a private message and I'll see if we can set something up. We (Cadence) have helped with a lot of VMM migrations now, so we can probably hel you out too :-)
In reply to StephenH:
I'm now using IUS 8.2
The errors above are corrected by using modefied version of VMM by Cadence.
But there are other errors in my SystemVerilog file.
Below are errors.
(ports is predefined interface and it doesn't irregurate SystemVerilog's convention.
why does error show? )
AhbMasterTest tb(ports); |ncvlog: *E,INNOTR (./TB_THOR.v,107|21): An instance name is not a legal rvalue [7.1(IEEE)]. module worklib.TB_THOR:v
In reply to Galguzimara:
From the error message, it is difficult to figure out the cause of the error. I did notice from your previous message that the VMM library version that you are using is: .../vmm-1.0.1/...; this indicates to me that this is not the version that was modified to work on IUS. Unles you changed the VMM library name, it should be something like: .../vmm-1.0.1-modius.../. Let me know the name of your company and I'll work with your application engineer to make sure that you have the latest version of the VMM library & also to help you with the migration process.