Error message during excuting ncverilog

I compiled very simple SystemVerilog file including VMM library with ncverilog just using +sv option

I found much error message in "vmm.sv" file and don't know what that means

I will show some part of the ncverilog log file below.

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ncverilog(64): 06.20-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
TOOL: ncverilog(64) 06.20-s005: Started on Mar 12, 2009 at 18:36:11 KST
ncverilog
 +access+rwc
 +incdir+/user/Galguzima/test/vmm-1.0.1/sv
 +sv
 simple_test.sv
file: simple_test.sv
                        const ref logic [7:0] unpack[]);
                            |
ncvlog: *E,FNDKWD (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|28): A SystemVerilog keyword was found where an identifier was expected.
(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2)
                        const ref logic [7:0] unpack[]);
                                      |
ncvlog: *E,ILLPDL (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|38): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2)
                        const ref logic [7:0] unpack[]);
                                                      |
ncvlog: *E,EXPSMC (/user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv,1146|54): expecting a semicolon (';') [3.2.2(IEEE)].
(`include file: /user/Galguzima/test/vmm-1.0.1/sv/std_lib/vmm.sv line 1146, `include file: /user/Galguzima/test/vmm-1.0.1/sv/vmm.sv line 21, file: simple_test.sv line 2)
   endfunction