Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I got following spice model for external MOSFET from the vandor, how can I import this into spectre to get the right simulation results.
I added "simulator lang=spice" line at the top, but it doesn't give me the right result.
MODEL REMOVED BY MODERATOR BECAUSE VENDOR MODEL REQUEST PAGE MAKES IT CLEAR THAT THE MODEL MAY NOT BE DISTRIBUTED.
We probably need more information to give a good answer...
Did you get any error messages from spectre?
How do you know the result isn't correct?
One thing... Did you encase your model file in:
<spice model file goes in here>
And include the model via a spectre include file.
As an aside, if you want to include a spice subcircuit into a schematic, see How to Simulate a Subcircuit (Netlist) With Spectre in ADE
Sr. Staff Support AE, Global Customer Support
Cadence Design Systems, Inc.
In reply to Tawna:
In reply to wenbo:
Putting it in the "Include Path" field is bound not to work, since that is a list of directories that it looks for relative files specified in the model files, stimulus file or definition files lists.
It really would help to see the warnings and errors you are getting - without that it's really hard to debug. I did see that there are some extremely small resistors (1u) and some of the sheet resistances in the MOSFET models are not good for spectre.
Overall, knowing the errors and warnings is much more likely to allow us to debug it.
Just had a thought - are you actually allowed to post the model on a public site? Most likely the model is owned by the vendor and you are breaking any license/NDA agreement you have by posting it here. Better would be to post a link to the vendor's site if it is available for public download.
In reply to Andrew Beckett:
There was no attachment. To add attachments, you need to do it via the web site - you can't (I believe) just add them to an email reply to the forum.
Here is the file.
A couple of things. You could try setting the global option minr to something smaller - say 0.1m . That should stop it filtering some of the small parasitic resistors inside the models.
However, I believe some of the problem may be caused by the floating nodes in the model - it talks about some of the nodes being floating. I can't check now because of having deleted the model from your original post in order not to violate Fairchild Semiconductor's conditions of use.
So, what I would suggest is:
Then there's a chance of being able to debug it.
The model was actually written for PSPICE, and as such takes advantage of some of the assumptions in PSPICE (which is more geared up for larger voltage off-chip circuits, whereas spectre is more geared up for typical IC problems). I see that Fairchild also provide BSIM3 based models for many of their transistors - but it appears not for this particular device.
excuse me if I bother you with a problem that was presented and apparently solved many times, but Spectre can't read the spice model of the component BF862. I followed in detail the post
but when the simulation starts, this error message appears:
Error (SFE-874) : ".../spice_BF862.prm" Unexpected end of line. Expected equals sign, numeric value or string value.
The model of the device can be downloaded freely at
This is the file I used:
Any suggestion would be really appreciated.
In reply to Steve88:
I removed the content of the model file that you posted above; it's NXP's model, so it should not be re-published on this forum.
The fundamental problem is that it isn't really in SPICE syntax. First of all, there's no .SUBCKT header - I was expecting that there would be something like:
.SUBCKT JBF862 1 2 3
at the top. Secondly, there's a bunch of L, R and C components, but no instantiation of the model - it just defines the model. So no transistor instance. And finally it doesn't have a "." before the last line. I'm not that familiar with PSPICE (this may be a PSPICE model), despite it being a Cadence product, and so I tried using the new "pspice_include" statement that is in MMSIM13.1 to see if that helps. It didn't, because even then I would expect it to have a .SUBCKT statement. I suspect this is a file that can be read into Orcad Capture and then used within that environment (again, not my product area).
So the best bet would probably be to contact customer support so we can explore this together in more detail; you might also need to contact the model vendor for some support.
thank you for the fast response. Excuse me again: I will contact the customer support as soon as possible.