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  3. How to transfer spice model to spectre model

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How to transfer spice model to spectre model

archive
archive over 15 years ago

I got following spice model for external MOSFET from the vandor, how can I import this into spectre to get the right simulation results.

I added "simulator lang=spice" line at the top, but it doesn't give me the right result.

MODEL REMOVED BY MODERATOR BECAUSE VENDOR MODEL REQUEST PAGE MAKES IT CLEAR THAT THE MODEL MAY NOT BE DISTRIBUTED.

 

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  • Andrew Beckett
    Andrew Beckett over 15 years ago

    Hi Wenbo,

    A couple of things. You could try setting the global option minr to something smaller - say 0.1m . That should stop it filtering some of the small parasitic resistors inside the models.

    However, I believe some of the problem may be caused by the floating nodes in the model - it talks about some of the nodes being floating. I can't check now because of having deleted the model from your original post in order not to violate Fairchild Semiconductor's conditions of use.

    So, what I would suggest is:

    1. Get permission from Fairchild Semiconductor to send the model to Cadence Customer Support (or ask them to send it)
    2. Get the model and testcase showing the problem to Cadence Customer Support - http://support.cadence.com

    Then there's a chance of being able to debug it.

    The model was actually written for PSPICE, and as such takes advantage of some of the assumptions in PSPICE (which is more geared up for larger voltage off-chip circuits, whereas spectre is more geared up for typical IC problems). I see that Fairchild also provide BSIM3 based models for many of their transistors - but it appears not for this particular device.

    Best Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 15 years ago

    Hi Wenbo,

    A couple of things. You could try setting the global option minr to something smaller - say 0.1m . That should stop it filtering some of the small parasitic resistors inside the models.

    However, I believe some of the problem may be caused by the floating nodes in the model - it talks about some of the nodes being floating. I can't check now because of having deleted the model from your original post in order not to violate Fairchild Semiconductor's conditions of use.

    So, what I would suggest is:

    1. Get permission from Fairchild Semiconductor to send the model to Cadence Customer Support (or ask them to send it)
    2. Get the model and testcase showing the problem to Cadence Customer Support - http://support.cadence.com

    Then there's a chance of being able to debug it.

    The model was actually written for PSPICE, and as such takes advantage of some of the assumptions in PSPICE (which is more geared up for larger voltage off-chip circuits, whereas spectre is more geared up for typical IC problems). I see that Fairchild also provide BSIM3 based models for many of their transistors - but it appears not for this particular device.

    Best Regards,

    Andrew.

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