Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Is it possible to tell spectre to save all nodes or terminal currents within a certain subckt? It's trivial in Hspice, you could do
save all Xtop.Xsub.*
I believe there's even a way to use the wildcards to get it to only do the top-level within that subcircuit, but I don't recall it..
Any ideas? How would it be done through the ADE, without messing with the netlist?
a quick >spectre -h save
will reveal that it is trivial in spectre as well:
Spectre has similar syntax - see "spectre -h save". So it's trivial in spectre too. You have to do it via an include file though in ADE. The reason is that the wildcards are based on the netlist names, rather than the schematic names - although I believe there's an enhancement request to add support for this on the UI.
You can (on the Options->Save All) choose to save voltages using "lvlpub" and then specify nestlvl - which means that it will save the top N levels of hierarchy. But if you only want to save lower levels, the best approach would be to have an include (included via Setup->Model Libraries, say) with a save statement in.
In reply to Andrew Beckett:
That's what I was hoping to hear.. this will help me a lot.
In reply to swdesigner:
How about AMS?
I find that the best way with spectre and the ADE is to put the full pathname of the include file in the Defintion files field under Simulation Files. (Model Libraries was suggested, but I think this is more meaningful).
Could someone post an example of save commands for AMS and the best location to specify the file for inclusion (which field in ADE to use)?
Referring to the use save-statement to save operating points for specify transistors located within a hierarchy. I had been using the include statement method (e.g., create a file and add the file via Setup->Model Libraries in Analog Design Environment window) but ran into problem with the use of wildcard.
In my test bench, I have a circuit block that is used five times within a hierarchy and they are name IDBA. I want to save the operating condition for a transition (P18) within the circuit block and I included this statement "save DUT.ILNA.IDBA\.P18:oppoint" hoping with the intention of having spectre save the operating points for the transistos P18 in all the five copies.
Unfortunately, the operating points for all five transistors were not saved and executing the command "OP("/IDUT.ILNA.IDBA.P18" "gm") returned nil. If I changed the save-statement to "save DUT.ILNA.IDBA\.P18:oppoint" then the OP command would return a number. Do I have to have a separate save-statement for each instance of IDBA? Or I have to use another symbol as a wild card?
In reply to slim5:
If the subckt (cell) name containing P18 is (say) "DBA" then you could do:
save P18:oppoint subckt=DBA sigtype=dev
then this would save P18 in all instances of DBA (i don't know what your cell is called)..
save *.IDBA.P18:oppoint sigtype=dev
Would do it.
How can we make spectre to save all the supply currents of all the blocks upto a certail depth of hierarchy?
The below save fail(I have useterms=name option set)
save I*.*:VDD* sigtype=all
save VDD*:currents sigtype=subckt
In reply to P K:
save *:VDD sigtype=subckt depth=2
Thanks it works for all terminals named VDD.
However, if i specify the following to match all my VDD terminals of the subckt(VDDA, VDDD,VDD_1P2V, and so on), the simulator exits with a segmentation fault(SPECTRE-18)
save *:VDD* sigtype=subckt depth=2
I'm not sure that having wildcards on the terminal name is supported, but it shouldn't crash regardless. I've filed CCR 1109175 to address this (and hopefully to support wildcards on the terminal name side since there's a clear need for this in this case).