Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hi, when I run a Monte Carlo analysis in Cadence Spectre-v 6.1.3 (process only), I'm looking for the variation effect on each nominal length (L effective) of the circuit's transistors. I find only the varied process data corresponding toa particular run but nothing about width or length chosen for a trial !Is there any way to do this please ?Another question : what the meaning of process data as wd108, wd015, and so on ? Thank you.
In reply to Quek:
Quek - you beat me to it!
In addition, it would only vary the length if the length of the devices was influenced by a parameter which had a statistical variation associated with it in a statistics block (see "spectre -h montecarlo") - and I've not seen that done very commonly in PDKs. Usually it's model parameters that are varied - although it could potentially be done with some of the model parameters that affect deltaW and deltaL - if so you'd be able to annotate the weff/leff parameters (from the same right mouse button menu that Quek pointed to) for a specific point - and then you'd be able to see on the schematic what the effective length for a specific device was. However, this assumes that the effective length was actually altered by the models. Note you'd probably also have to use the Edit->Component Display form to alter what is annotated on the schematic.
BTW, stating what PDK you're using might mean that somebody familiar with that specific PDK might be able to give some more detailed advice - but the documentation for the PDK is a good place to start.
In reply to Andrew Beckett:
Thanks for your quick reply !I don't see the detail view but only the default view ! Unfortunately, the 'print statistical Parameters' on the default view and the 'result Browser' give me anything about leff or weff. Do you know where could I possibly find documentation about the way to display parameters data as leff?Thanks !
In reply to inessadm:
You must be using an old version (e.g. 6.1.3 or 6.1.2) because it was renamed from Default to Detailed some time ago.
Anyway, as I said, you won't see leff in the statistical parameters if it is not being statistically varied.
I was mistaken about annotating it on the schematic. The leff should be in the "output" parameters in the result browser - you can enter this expression in the calculator and then plot it (assuming you've saved family data on the Monte Carlo options form):
pv("/I7/M3" "leff" ?result 'output)
Note that /I7/M3 is the hierarchical path to the device in the schematic. If I do this, I see the effective length of that transistor versus the iteration number. In my case it doesn't vary because it's not a statistical parameter...
I've got only "dc operating points" or "design parameters" folders but anything about "outputs parameters" in my result browser ! I have to add specific option to view it ?inessadm
Double click on the test name in ADE XL to bring up the Test Editor, and then do Outputs->Save All. I suspect that "Save output parameters info" has been turned off.
That said, this is extremely unlikely to help you, because the chances are the length is not being altered by the statistical models.