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HI, I am trying to perform a mixed signal simulation using spectreVerilog. Now if I give sdf file in mixed signal options of ADE, I get the following error and sdf's timing related data is not incorported in digital netlist. what should I do? SDFA Error: Unable to find instance test.top.\1 .G24*** End of SDF back-annotation 1 Verilog-XL SDF Annotator error
Very hard to advise given the lack of information, but maybe there's a mapping problem caused by the fact that you appear to have an instance name with a numerical name ("1") inside top. Try giving it a name that is a legal verilog identifier (e.g. "I1") and see if that helps (of course, the SDF file will need to match).
Is there a good reason why you're using spectreVerilog? It's using obsolete technology and is really superseded by "AMS Designer" (ams in the choice of simulators in ADE). That's based around the Incisive (ncsim) simulators, and not the very old Verilog-XL.
In reply to Andrew Beckett:
Thanks Adrew, Problem is solved and "I" was missing in the scope.Now I have another design in which some registers are present. SDF writes timing for a reg as follows:(CELL (CELLTYPE "DFFNQ_X3M_A12TS_C31") (INSTANCE count_reg\[3\]) (DELAY (ABSOLUTE (IOPATH (negedge CKN) Q (0.099::0.099) (0.085::0.085)) ) ) (TIMINGCHECK (WIDTH (COND ENABLE_D==1'b1 (posedge CKN)) (0.120::0.120)) (WIDTH (COND ENABLE_D==1'b1 (negedge CKN)) (0.039::0.039)) (WIDTH (COND ENABLE_NOT_D==1'b1 (posedge CKN)) (0.071::0.071)) (WIDTH (COND ENABLE_NOT_D==1'b1 (negedge CKN)) (0.038::0.038)) (SETUPHOLD (posedge D) (negedge CKN) (0.057::0.057) (0.011::0.011)) (SETUPHOLD (negedge D) (negedge CKN) (0.041::0.041) (-0.018::-0.018)) ) )
compiler uses this as input and turns it into something as follows:(CELL (CELLTYPE "DFFNQ_X3M_A12TS_C31") (INSTANCE test.top.I0.count_reg\[3\]) (DELAY (ABSOLUTE (IOPATH (negedge CKN) Q (0.099::0.099) (0.085::0.085)))) (TIMINGCHECK (WIDTH (COND ENABLE_D == 1'b1 (posedge CKN)) (0.120::0.120)) (WIDTH (COND ENABLE_D == 1'b1 (negedge CKN)) (0.039::0.039)) (WIDTH (COND ENABLE_NOT_D == 1'b1 (posedge CKN)) (0.071::0.071)) (WIDTH (COND ENABLE_NOT_D == 1'b1 (negedge CKN)) (0.038::0.038)) (SETUPHOLD (posedge D) (negedge CKN) (0.057::0.057) (0.011::0.011)) (SETUPHOLD (negedge D) (negedge CKN) (0.041::0.041) (-0.018::-0.018))))Now when I run the simulation following error occurs:*** SDF Annotator version 2.3.3 *** SDF Interface version TOOL: libsdfi 08.20-d001 *** SDF file: /home/aanjum/simulation/DLL_tb/spectreVerilog/config/netlist/digital/sdf_mar28_dll_2_1_I0 *** Back-annotation scope: test.top *** Configuration file: /home/aanjum/simulation/DLL_tb/spectreVerilog/config/netlist/digital/sdf.cfg *** SDF Annotator log file: /home/aanjum/simulation/DLL_tb/spectreVerilog/config/netlist/digital/sdf_mar28_dll_2_1_I0.sdflog *** MTM selection parameter specified: MINIMUM *** SCALE FACTORS parameter specified: 1.000000:1.000000:1.000000 *** No SCALE TYPE parameter specified Configuring for back-annotation... Reading SDF file and back-annotating timing data... /home/aanjum/simulation/DLL_tb/spectreVerilog/config/netlist/digital/sdf_mar28_dll_2_1_I0 L183: SDFA Error: Unable to find instance test.top.I0.\count_reg *** End of SDF back-annotation 4 Verilog-XL SDF Annotator errors
Now if I change count_reg\[3\] to count_reg, the error disappears. What should I do other than manually editing sdf?
In reply to Arslan:
Well, if the names in the SDF don't match the names in the design, you'll have to fix them! You can only use escaped names if the verilog name is escaped too - which I doubt it would be for such a name.
So I'd say you need to fix the SDF.