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SDF Error

Arslan

HI, I am trying to perform a mixed signal simulation using spectreVerilog. Now if I give sdf file in mixed signal options of ADE, I get the following error and sdf's timing related data is not incorported in digital netlist. what should I do?

 SDFA Error: Unable to find instance test.top.\1 .G24

*** End of SDF back-annotation
1 Verilog-XL SDF Annotator error

Parents
  • Andrew Beckett

    Well, if the names in the SDF don't match the names in the design, you'll have to fix them! You can only use escaped names if the verilog name is escaped too - which I doubt it would be for such a name.

    So I'd say you need to fix the SDF.

    Andrew.

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  • Andrew Beckett

    Well, if the names in the SDF don't match the names in the design, you'll have to fix them! You can only use escaped names if the verilog name is escaped too - which I doubt it would be for such a name.

    So I'd say you need to fix the SDF.

    Andrew.

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