Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
For analog design, I have not seen too many people make use of pcells for schematics or symbols.Are you using pcells for schematics or pcells, especially for analog design? If so, what is the basic function of the pcell? Why did you choose a pcell instead of a static cell?Thanks!
I have created both schematic and symbol pcells. Some examples:I have a transistor symbol which can either be a 3 or 4 terminal mosfet, controlled by a property on the pcell. If the user chooses 3 terminals, then the 4th terminal is found via an inherited connection terminal on the stopping (e.g. spectre) view - but they don't need to wire it up. If the user chooses 4 terminals then all 4 terminals are present on the symbol.Another example is a component for driving a bus with a constant value. This has parameters for the value and the bus width. This is implemented with both a schematic and a symbol pcell. The symbol pcell merely changes the terminal/pin to be a bus with variable width; the schematic pcell instantiates a variable number (depending on the bus width parameter) of "cds_thru" components to create connections from either a high input or a low input to the particular bit of the bus - which connection is made depends on the value parameter of the pcell.Another schematic pcell is for a series-connected resistor. I wanted a resistor with an "s-factor", so that the voltage dependency on a number of series connected resistors could be modelled properly (there are other ways of solving this, but this was more of an illustration). So it divides the resistor value by the s-factor, and places s resistors with that divided value, connected in series.That's some simple examples of what they can be useful for.Note with schematic pcells there's no need to create the graphical representation of the schematic - just the connectivity information will do.Regards,Andrew.
In a previous life, we were working with a process which was yet to be fully qualified, and for which there were no PDKs, so I wrote the pCells for layout and schematics.
Using common code between the schematic symbol and layout views allowed me to know the exact dimensions of the component given appropriate parameters (FET width and length, resistor value, capacitor value), from which parasitic effects could be determined and annotated onto the device for netlisting (via CDF parameters) eg. FET AS/AD/PS/PD, resistor parasitic cap, capacitor bottom plate cap, etc.
We had very good agreement between schematic simulation and RCX extracted simulation (and final silicon) at and above 6GHz, and our design cycles were tighter because we didn't need to go around the RCX loop as often.
With proper parameterized spectre/spice models, or a decent PDK, you don't need to do this. But if you want to work outside those models, nothing beats it.