Verilog-A, one time execution function

It might help if you gave more detail as to what you're trying to do - i.e. the code you tried. In general if you want something just to execute once, you could have some kind of state variable which starts off at 0, and then you set it to 1 once you've executed the code - and have the code check that the value of the variable is 0 before executing it.

However, there's probably little point giving an example of that because the problem you are having may be related to some other detail of the model - it's not clear.

So please show what you've tried, so folks here can give you a steer in the right direction.

Regards,

Andrew.

Thanks Andrew for you reply. Here is the code:

// VerilogA for demo, memr_model_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module memr_model_test (p, n);

inout p; //positive pin
inout n; //negative pin
electrical p, n;



// SUNY parameters
parameter real HRS = 1.5e5; // high resistance state
parameter real LRS = 1e4; // low resistance state
parameter real Vtp = 0.75; // positive threshold voltage
parameter real Vtn = -1.0; // negative threshold voltage
parameter real tsw_p = 1e-8; // time to switch under +V bias
parameter real tsw_n = 1e-6; // time to switch under -V bias



parameter real form = 0;


//poly parameters

parameter real CLRS = 1;

parameter real CHRS = 1;

parameter real P_LRS = 1;
parameter real P_HRS = 1;


parameter real Rinit = 1e4;//1e6;
parameter real Rpre = 1e4;//1e6;


real delR;
real time_last;
real Vwr;
real Iwr;
real delt;
real Rm;
real Rm_tmp;
real delRm;
real HRS_nom; // nominal high res, trends down w/ time
real LRS_nom;
real delI;
real I_last;
real f;
real tmp;

analog begin
@ ( initial_step or initial_step("dc") ) begin
delt = 0;
time_last = 0;
delI = 0;
I_last = 0;

f = form;

HRS_nom = HRS;
LRS_nom = LRS;



Rm = Rinit;

delR = HRS_nom - LRS_nom;



end

delt = $abstime - time_last;
time_last = $abstime;
Vwr = V(p,n);
delI = I(p,n)-I_last;
I_last = I(p,n);

@ (cross (I(p,n)-220e-6, +1))begin
LRS_nom = LRS_nom - (1e9/1e-6)*delI*delt/tsw_p;
if (LRS_nom < 0.5 *LRS)begin
LRS_nom = 0.5*LRS;
end
HRS_nom = HRS_nom - (1e9/1e-6)*delI*delt/tsw_p;

if (HRS_nom < 2 *LRS)begin
HRS_nom = 2*LRS;
end


end

//////////////////////////////// Executes only once

if (Vwr > 2.3)begin

tmp =1;
end

if (tmp==1)begin

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
f = 1;
tmp = 0;
end
end
//////////////////////////////////END


if (f == 1)begin

if (Vwr >= Vtp && Rm != LRS_nom) begin //Vtp

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
end

end

else if (Vwr < Vtn && Rm != HRS_nom) begin //Vtn
Rm_tmp = Rm + delt* CHRS * (delR/tsw_n) *(pow(((Vwr-Vtn)/Vtn), P_HRS)) ;

if (Rm_tmp >= HRS_nom) begin
Rm_tmp = HRS_nom;

end
end

else begin
Rm_tmp = Rm;
end


end









Rm = Rm_tmp;
I(p,n) <+ Vwr / Rm;

end // end analog


endmodule




It says it does not converge as follows:


************************************************
Transient Analysis `tran': time = (0 s -> 20 us)
************************************************
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
1 V0:p
1 I7:p_n_flow
1 T0:int_d
1 T0:int_s
1 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
1 I7:p_n_probe
1 T0:int_d
1 T0:int_s
1 net6

Trying `homotopy = gmin' for initial conditions.
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
5 V0:p
5 I7:p_n_flow
5 T0:int_d
5 T0:int_s
5 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
5 I7:p_n_probe
5 T0:int_s
5 net6

Trying `homotopy = source' for initial conditions.
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
8 V0:p
8 I7:p_n_flow
8 T0:int_d
8 T0:int_s
8 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
8 I7:p_n_probe
8 T0:int_d
8 T0:int_s
8 net6

Trying `homotopy = dptran' for initial conditions...
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
5 V0:p
5 I7:p_n_flow
5 T0:int_d
5 T0:int_s
5 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
5 I7:p_n_probe
5 T0:int_d
5 T0:int_s
5 net6

Trying `homotopy = ptran' for initial conditions..
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
5 V0:p
5 I7:p_n_flow
5 T0:int_d
5 T0:int_s
5 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
5 I7:p_n_probe
5 T0:int_s
5 net6

Trying `homotopy = arclength' for initial conditions.
None of the instantiated devices support arclength homotopy. Skipping.
Top 9 Solution Convergence failure counts accumulated from the beginning of simulation:
5 V0:p
5 I7:p_n_flow
5 T0:int_d
5 T0:int_s
5 net6
Top 9 Residue Convergence failure counts accumulated from the beginning of simulation:
5 I7:p_n_probe
5 T0:int_s
5 net6


Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (SPECTRE-16080): No DC solution found (no convergence).

The values for every node on the last Newton iteration are given below. For those nodes that did not converge, the manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol

Top 9 Solution too large Convergence failure:
I(V0:p) = 0 A
update too large: | -329.989 kA | > 0 A + 1 pA
I(I7:p_n_flow) = 0 A
update too large: | 329.989 kA | > 0 A + 1 pA
V(net6) = 0 V
update too large: | 1 kV | > 0 V + 1 uV
V(T0:int_d) = 0 V
update too large: | 1 kV | > 0 V + 1 uV
V(T0:int_s) = 0 V
update too large: | 1 kV | > 0 V + 1 uV
Top 9 Residue too large Convergence failure:
V(I7:p_n_probe) = 0 V
residue too large: | -329.989 kA | > 1.64995 kA + 1 pA
V(net6) = 0 V
residue too large: | 10.066 mA | > 50.33 uA + 1 pA
V(T0:int_s) = 0 V
residue too large: | 617.284 A | > 3.08642 A + 1 pA

Please comment your code (with explanation as to what each variable is for, and what each section does) - and indent it to make it readable. Right now it's too hard to try to figure out what it's doing (and what the intent is), so I'm afraid I can't spend the time figuring that out for you - it would take a large amount of time to try to unravel what you're actually trying to do here.

If doing that on the full code is too much effort, please provide a simpler (commented and properly indented) example that illustrates what you're trying to achieve.

Thanks,

Andrew.

Thanks Andrew
I added comments and indented.


// VerilogA for demo, memr_model_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module memr_model_test (p, n);

inout p; //positive pin
inout n; //negative pin
electrical p, n;



// SUNY parameters
parameter real HRS = 1.5e5; // high resistance state
parameter real LRS = 1e4; // low resistance state
parameter real Vtp = 0.75; // positive threshold voltage
parameter real Vtn = -1.0; // negative threshold voltage
parameter real tsw_p = 1e-8; // time to switch under +V bias
parameter real tsw_n = 1e-6; // time to switch under -V bias



parameter real form = 0; ///////////// This is a parameter assigned to a flag "f" later


//poly parameters

parameter real CLRS = 1;

parameter real CHRS = 1;

parameter real P_LRS = 1;
parameter real P_HRS = 1;


parameter real Rinit = 1e4;//1e6;
parameter real Rpre = 1e4;//1e6;


real delR;
real time_last;
real Vwr;
real Iwr;
real delt;
real Rm;
real Rm_tmp;
real delRm;
real HRS_nom; // nominal high res, trends down w/ time
real LRS_nom;
real delI;
real I_last;
real f;
real tmp;

analog begin
@ ( initial_step or initial_step("dc") ) begin
delt = 0;
time_last = 0;
delI = 0;
I_last = 0;

f = form;

HRS_nom = HRS;
LRS_nom = LRS;



Rm = Rinit;

delR = HRS_nom - LRS_nom;



end

delt = $abstime - time_last;
time_last = $abstime;
Vwr = V(p,n);
delI = I(p,n)-I_last;
I_last = I(p,n);

@ (cross (I(p,n)-220e-6, +1))begin
LRS_nom = LRS_nom - (1e9/1e-6)*delI*delt/tsw_p;
if (LRS_nom < 0.5 *LRS)begin
LRS_nom = 0.5*LRS;
end
HRS_nom = HRS_nom - (1e9/1e-6)*delI*delt/tsw_p;

if (HRS_nom < 2 *LRS)begin
HRS_nom = 2*LRS;
end


end
////////////////////////////until here, everything is fine
//////////////////////////////////////////////////////////////////////////////////////// HERE is the important part"
//////////////////////////////// this if (==0).....end Executes only once: This function is executed first as long as the flag is zero. Once the flag goes one, I want the simulation to ///////////////////switch to the other functions and remains there throughout the rest of the simulation time.


/////////////////////// once the Vwr hits 2.3, Rm should start decreasing. Once it hits LRS_nom, f is raised to "1" and this function is terminated.
if(f==0)
if (Vwr > 2.3)begin
tmp =1;
end

if (tmp==1)begin

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
f = 1;
tmp = 0;
end
end
end
//////////////////////////////////END

//////////////////////// This one works fine if I initialize form as "1". The simulation works normally
if (f == 1)begin

if (Vwr >= Vtp && Rm != LRS_nom) begin //Vtp

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
end

end

else if (Vwr < Vtn && Rm != HRS_nom) begin //Vtn
Rm_tmp = Rm + delt* CHRS * (delR/tsw_n) *(pow(((Vwr-Vtn)/Vtn), P_HRS)) ;

if (Rm_tmp >= HRS_nom) begin
Rm_tmp = HRS_nom;

end
end

else begin
Rm_tmp = Rm;
end


Rm = Rm_tmp;
I(p,n) <+ Vwr / Rm;

end // end analog


endmodule - See more at: community.cadence.com/.../1351165

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

That's barely any better. I can see that the if(f==0) line doesn't have a "begin" which looks wrong, but the code is so hard to read that I can't do more debugging.

I suggest you format it better and contact customer support.

Regards,

Andrew.

OK. I write here a simple code describing my code structure:
///////////////////////////////////////////////////////////////////begin code:
some initialization:
....
.... parameter real form = 0; // I initialize it as 0 or 1
.....
..... real f; // f is a flag
analog begin
@ ( initial_step or initial_step("dc") ) begin
....some dc initialization;
f=form;
end // end dc initialization

//////////////// here is the one time execution function
if (f==0)begin
.......... some code;
if (function is executed successfully)begin
f=1;
end
end
//////////////// end the one time execution function
if (f==1)begin
.... Run this part for the rest of the simulation time;
end

end // end analog

////////////////////////// End code
Note that I only run into DC convergence error when I start the simulation with f=0. if I start with f=1, the simulation runs normally. Do you think there is something wrong with the code structure?

Thanks!