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Verilog-A, one time execution function

Hi,

I am developing a verilog-A model for a device. I want to write a function that is executed only one time in the simulation during the device first transition from high resistive state to a low resistive state. I looked at analog events but did not find a function that provides this functionality I want. I tried to do it using an if..else statement but it gave me convergence error.

Can someone help me with that?

Thanks

Parents

samer1 over 8 years ago

Thanks Andrew
I added comments and indented.

// VerilogA for demo, memr_model_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module memr_model_test (p, n);

inout p; //positive pin
inout n; //negative pin
electrical p, n;

// SUNY parameters
parameter real HRS = 1.5e5; // high resistance state
parameter real LRS = 1e4; // low resistance state
parameter real Vtp = 0.75; // positive threshold voltage
parameter real Vtn = -1.0; // negative threshold voltage
parameter real tsw_p = 1e-8; // time to switch under +V bias
parameter real tsw_n = 1e-6; // time to switch under -V bias

parameter real form = 0; ///////////// This is a parameter assigned to a flag "f" later

//poly parameters

parameter real CLRS = 1;

parameter real CHRS = 1;

parameter real P_LRS = 1;
parameter real P_HRS = 1;

parameter real Rinit = 1e4;//1e6;
parameter real Rpre = 1e4;//1e6;

real delR;
real time_last;
real Vwr;
real Iwr;
real delt;
real Rm;
real Rm_tmp;
real delRm;
real HRS_nom; // nominal high res, trends down w/ time
real LRS_nom;
real delI;
real I_last;
real f;
real tmp;

analog begin
@ ( initial_step or initial_step("dc") ) begin
delt = 0;
time_last = 0;
delI = 0;
I_last = 0;

f = form;

HRS_nom = HRS;
LRS_nom = LRS;

Rm = Rinit;

delR = HRS_nom - LRS_nom;

end

delt = $abstime - time_last;
time_last = $abstime;
Vwr = V(p,n);
delI = I(p,n)-I_last;
I_last = I(p,n);

@ (cross (I(p,n)-220e-6, +1))begin
LRS_nom = LRS_nom - (1e9/1e-6)*delI*delt/tsw_p;
if (LRS_nom < 0.5 *LRS)begin
LRS_nom = 0.5*LRS;
end
HRS_nom = HRS_nom - (1e9/1e-6)*delI*delt/tsw_p;

if (HRS_nom < 2 *LRS)begin
HRS_nom = 2*LRS;
end

end
////////////////////////////until here, everything is fine
//////////////////////////////////////////////////////////////////////////////////////// HERE is the important part"
//////////////////////////////// this if (==0).....end Executes only once: This function is executed first as long as the flag is zero. Once the flag goes one, I want the simulation to ///////////////////switch to the other functions and remains there throughout the rest of the simulation time.

/////////////////////// once the Vwr hits 2.3, Rm should start decreasing. Once it hits LRS_nom, f is raised to "1" and this function is terminated.
if(f==0)
if (Vwr > 2.3)begin
tmp =1;
end

if (tmp==1)begin

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
f = 1;
tmp = 0;
end
end
end
//////////////////////////////////END

//////////////////////// This one works fine if I initialize form as "1". The simulation works normally
if (f == 1)begin

if (Vwr >= Vtp && Rm != LRS_nom) begin //Vtp

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
end

end

else if (Vwr < Vtn && Rm != HRS_nom) begin //Vtn
Rm_tmp = Rm + delt* CHRS * (delR/tsw_n) *(pow(((Vwr-Vtn)/Vtn), P_HRS)) ;

if (Rm_tmp >= HRS_nom) begin
Rm_tmp = HRS_nom;

end
end

else begin
Rm_tmp = Rm;
end

Rm = Rm_tmp;
I(p,n) <+ Vwr / Rm;

end // end analog

endmodule - See more at: community.cadence.com/.../1351165

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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samer1 over 8 years ago

Thanks Andrew
I added comments and indented.

// VerilogA for demo, memr_model_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module memr_model_test (p, n);

inout p; //positive pin
inout n; //negative pin
electrical p, n;

// SUNY parameters
parameter real HRS = 1.5e5; // high resistance state
parameter real LRS = 1e4; // low resistance state
parameter real Vtp = 0.75; // positive threshold voltage
parameter real Vtn = -1.0; // negative threshold voltage
parameter real tsw_p = 1e-8; // time to switch under +V bias
parameter real tsw_n = 1e-6; // time to switch under -V bias

parameter real form = 0; ///////////// This is a parameter assigned to a flag "f" later

//poly parameters

parameter real CLRS = 1;

parameter real CHRS = 1;

parameter real P_LRS = 1;
parameter real P_HRS = 1;

parameter real Rinit = 1e4;//1e6;
parameter real Rpre = 1e4;//1e6;

real delR;
real time_last;
real Vwr;
real Iwr;
real delt;
real Rm;
real Rm_tmp;
real delRm;
real HRS_nom; // nominal high res, trends down w/ time
real LRS_nom;
real delI;
real I_last;
real f;
real tmp;

analog begin
@ ( initial_step or initial_step("dc") ) begin
delt = 0;
time_last = 0;
delI = 0;
I_last = 0;

f = form;

HRS_nom = HRS;
LRS_nom = LRS;

Rm = Rinit;

delR = HRS_nom - LRS_nom;

end

delt = $abstime - time_last;
time_last = $abstime;
Vwr = V(p,n);
delI = I(p,n)-I_last;
I_last = I(p,n);

@ (cross (I(p,n)-220e-6, +1))begin
LRS_nom = LRS_nom - (1e9/1e-6)*delI*delt/tsw_p;
if (LRS_nom < 0.5 *LRS)begin
LRS_nom = 0.5*LRS;
end
HRS_nom = HRS_nom - (1e9/1e-6)*delI*delt/tsw_p;

if (HRS_nom < 2 *LRS)begin
HRS_nom = 2*LRS;
end

end
////////////////////////////until here, everything is fine
//////////////////////////////////////////////////////////////////////////////////////// HERE is the important part"
//////////////////////////////// this if (==0).....end Executes only once: This function is executed first as long as the flag is zero. Once the flag goes one, I want the simulation to ///////////////////switch to the other functions and remains there throughout the rest of the simulation time.

/////////////////////// once the Vwr hits 2.3, Rm should start decreasing. Once it hits LRS_nom, f is raised to "1" and this function is terminated.
if(f==0)
if (Vwr > 2.3)begin
tmp =1;
end

if (tmp==1)begin

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
f = 1;
tmp = 0;
end
end
end
//////////////////////////////////END

//////////////////////// This one works fine if I initialize form as "1". The simulation works normally
if (f == 1)begin

if (Vwr >= Vtp && Rm != LRS_nom) begin //Vtp

Rm_tmp = Rm - delt* CLRS* (delR/tsw_p)*( pow(((Vwr-Vtp)/Vtp), P_LRS));

if (Rm_tmp <= LRS_nom) begin

Rm_tmp = LRS_nom;
end

end

else if (Vwr < Vtn && Rm != HRS_nom) begin //Vtn
Rm_tmp = Rm + delt* CHRS * (delR/tsw_n) *(pow(((Vwr-Vtn)/Vtn), P_HRS)) ;

if (Rm_tmp >= HRS_nom) begin
Rm_tmp = HRS_nom;

end
end

else begin
Rm_tmp = Rm;
end

Rm = Rm_tmp;
I(p,n) <+ Vwr / Rm;

end // end analog

endmodule - See more at: community.cadence.com/.../1351165

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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