Creating a master slave current mirror

One way to do this is to use a design parameter for the W and L using the same parameter for each transistor, e.g. parameters cmL and cmW - the values for these could be set in the simulation environment (ADE).

Design variables are probably the way to go for this, and this would give you the added benefit of being able to run parametric analysis on the cmL and cmW parameters.

An alternative might be to create an extra level of hierarchy so that you have at least these two transistors in a new cell. On the transistor instances you would use the pPar() function to refer to a named parameter on the parent (again let's say cmL and cmW), for example pPar("cmL") for the "l" (ell) parameter of both instances, and pPar("cmW") for the "w" parameter on each instance. When you create a symbol for this new cell (Design -> Create Cellview -> From Cellview) the automatic symbol generator will automatically create the two CDF parameters so that when you place an instance of the new cell, these parameters are present on the Add Instance for, or the Edit Object Properties form.

Regards.