how can we calculate leakage current of a circuit in cadence spectre simulator. please help me.
What type of leakage current? Gate leakage? Subthreshold conduction? Are you designing in CMOS? Are you characterizing a single gate or a whole design? How accurate do you need it to be? If you want help, I'd encourage you to be as specific as possible.
Here are some thoughts:
1) If you have a large digital design block, and you are looking at the non-dynamic power, bias the thing up, get it in a known stable state, and stop the clocks. Plot the current until it reaches a stable state. That is your static power dissipation, which included gate leakage, and subthreshold conduction.
2) If you are looking at gate leakage for a process, bias a transistor and plot the dc current flowing into the gate.
3) If you are looking at subthreshold conduction leakage, step through the possible inputs and output states and look at the drain current when the circuit is at steady state.
These are all pretty generic. To save a current in the analog design environment, use the menu option Outputs -> To Be Saved -> Select on schematic and click on the pin of the device that you want to plot the current.