I'm going to create a transistor with coded in subckt. However, if i draw a schematic on in cadence, when simulate it by hspice, it will automatically add a 'M' for my transistor. but in order to simulate a subckt, the parameter should be 'X'. Is it possible to create a new component with sub circuit? if yes, how to make it automatically appeared a 'X' in the netlist?
You have to change the 'namePrefix' in your
netlister/simulator 'Simulation Information'
of your cell CDF (Component Description Format).
If you not familiar with this browse the docs for 'CDF' or
experimetn with 'CIW->Tools->CDF->Edit..'.