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VCAR single vias on pins

Hi guys, please feel free to point me the correct forum, this is a custom layout question but i can't find a more appropriate place to post it yet:

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I'm finding that on a given VCAR routed net that at its end point where is meets the pin, if there is a via directly on the pin it is single (1x1) even though i have specified 2x1 vias for all nets. If i trace such a net there are multiple vias(2x1) at all other metal jumps. Here is my .do commands:

unselect all nets
select all nets
define (class myNets (selected))
unselect all nets
circuit class myNets (use_via (use_array M2_M1 1 2) (use_array M3_M2 1 2) (use_array M4_M3 1 2))
rule ic (stack_via any_overlap)

Thanks in advance

Stu

stuso over 16 years ago

The best solution i can find so far is to widen pins to at least the size of of a 2x2 via, this seems to do the trick.
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