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  3. SOC Encounter: Problem with multiple clocks

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SOC Encounter: Problem with multiple clocks

Sirrius
Sirrius over 16 years ago

 Hello All,

 I have a design that involves two clocks (clk and sh_clk). However, after encounter synthesizes my design, it "splits" my clocks.

The design consists of a kernel (Braun_Multiplier) and a wrapper for pads (Braun_Multiplier_WithPads), The input design header for the core reads:

module Braun_Multiplier(A_in, B_in, clk, sh_clk, clear, mult_output, cmp_out);

While the header for the core in the nelist generated by Encounter reads:

 module Braun_Multiplier (
    A_in,
    B_in,
    clk,
    sh_clk,
    clear,
    mult_output,
    cmp_out,
    clk_at_Pad__L2_N1,
    clk_at_Pad__L2_N2,
    clk_at_Pad__L2_N3 );


 I do not understand why the clk signal should be "split" like shown here. I am not sure whether this is correct or not.

 However, at the highest level of design (Braun_Multiplier_WithPads), the input design header to Enounter is:

module Braun_Multiplier_WithPads(A_ChipInp, B_ChipInp, clk_ChipInp,
     sh_clk_ChipInp, clear_ChipInp, mult_output_ChipOutp,
     cmp_out_ChipOutp);


 and in the netlist generated by Encounter, it is:

module Braun_Multiplier_WithPads (
    A_ChipInp,
    B_ChipInp,
    clk_ChipInp,
    sh_clk_ChipInp,
    clear_ChipInp,
    mult_output_ChipOutp,
    cmp_out_ChipOutp );


So, there seems to be consistency here.

In my synthesis script for Encounter, I have these lines:

setClockDomains -all \
  -clk clk sh_clk\
  -event R


 Can someone please point out to me whether this may be a problem? And if yes, what step will rectify it?

I wanted to attach the entire script that I use for synthesis, but, couldn't find "attach" option :(

 Thanks

 

Sirrius

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  • Austin CAD Guy
    Austin CAD Guy over 16 years ago

    This is the Custom IC (Virtuoso) forum and you will probably do better by posting this in the digital forum.

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  • Sirrius
    Sirrius over 16 years ago
    Done! Thanks for the suggestion
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