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Simulating the verilog +Analog

Stud ent

Hi,

   I am planning to do a transient sim on top level. I have my analog blocks aswell as  (digital) verilog files. How can I put them together

in one sim? Any help would be much appreciated.

Thanks...

  • The best way to do this is to use "AMS Designer". This is a mixed-signal simulator that supports multiple languages (all the languages that Incisive supports, as well as Verilog-AMS and VHDL-AMS).

    Look at <ICinstDir>/doc/amsenvug/amsenvug.pdf for some details. The ADE interface is also covered in the <ICinstDir>/doc/anasimhelp/anasimhelp.pdf

    You might want to look at the "AVUM" workshop in <ICinstDir>/ tools/dfII/samples/tutorials/AMS

    Regards,

    Andrew.

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