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VerilogA Problem in MMSIM-7.1

gokce

Hi,

 I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get:

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi/Linux2.6.11.4-21.9-smp+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

 In  ahdlcmi.out, I get:

/usr/cds/mmsim-7.1/tools.lnx86/systemc/gcc/4.1/bin/gcc  -march=i486 -ffast-math -O3 -DSYSV -DSVR4 -D_REENTRANT -fPIC   -DconfigSPECTRE -I. -I/usr/cds/mmsim-7.1/tools.lnx86/spectre/ahdlcmi/include -c BinSearch_DcFuncDerLoad.c -o obj/optimize/5.0/BinSearch_DcFuncDerLoad.o || rm -f -f obj/optimize/5.0/BinSearch_DcFuncDerLoad.o;
gcc: error trying to exec 'cc1': execvp: No such file or directory

I attached the log files. Does anyone have an idea?

 

Thanks,

Gokce

netlist.zip
Parents
  • Winglet

    Hello Andrew!

    I have some good news regarding this topic.

    The problem was that we could simulate some verilog blocks but it fails with 3 specific ones. Then, we tried to simulate those ones in another computer where we have Cadence installed, and it worked. The diference between those machines is that we have an older version of MMSIM (7.01) where it worked, and a latter version (7.11) where it wasn't.

    I checked it by installing the older version of MMSIM in the first machine and then I switched the "environment PATH" between older and newer version of MMSIM. Then I confirmed that:

    MMSIM 7.11HF188 - Not working for us. We have the described problem.

    MMSIM 7.01HF076 - Working correctly.

    Anyway, I don't know nothing about verilog because I work with schematics and layouts, so I still have to talk with my mate and confirm all of this. After that, I will post any news.

    Regards,
    Marcos.

Reply
  • Winglet

    Hello Andrew!

    I have some good news regarding this topic.

    The problem was that we could simulate some verilog blocks but it fails with 3 specific ones. Then, we tried to simulate those ones in another computer where we have Cadence installed, and it worked. The diference between those machines is that we have an older version of MMSIM (7.01) where it worked, and a latter version (7.11) where it wasn't.

    I checked it by installing the older version of MMSIM in the first machine and then I switched the "environment PATH" between older and newer version of MMSIM. Then I confirmed that:

    MMSIM 7.11HF188 - Not working for us. We have the described problem.

    MMSIM 7.01HF076 - Working correctly.

    Anyway, I don't know nothing about verilog because I work with schematics and layouts, so I still have to talk with my mate and confirm all of this. After that, I will post any news.

    Regards,
    Marcos.

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