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Spectre Simulation using IBM_PDK and ARM Std Cell Libraries

canuck

I'm trying to do a simple Spectre simulation with a few elements (symbols) from the ARM Std Cell library and I'm having some difficulties. First I just received the ARM library package and it includes (for every cell):

1. symbol view

2. cmos_sch view (with input and output pins)

3. a large common CDL netlist file (including all stdcell elements)  in SPICE format

4. a large common  LPE (with parasitics) netlist file (including all stdcell elements) in SPICE format

5. NO SCHEMATIC VIEW for the std cells

I can hack the netlist and make the simple simulation work (see 2 hacks below), but I don't want to do this everytime. The automatically generated Spectre netlist should look like one of the 2 netlists below (which I both hacked).I want to be able to use any symbol from the std cell library in a schematic and have a correct Spectre netlist generated. 

Note: Both following netlists have been hacked and I want this to work automatically using the Virtuoso ADE interface.

-------Hacked Netlist 1 (subcircuit inserted in body, no include file) 

simulator lang=spectre
global 0 gnd vdd
include "/remote/eeserv01/software/cadence/Technology/IBM_PDK/cmrf8sf/V1.6.0.3DM/Spectre/models/allModels.scs"

// Library name: ARM_ibm13rf_reg
// Cell name: INVX4TF
// View name: cmos_sch
subcircuit INVX4TF A Y
M0 vdd a y vdd pfet W=2.34U L=0.12U M=1
M1 y a gnd gnd nfet W=1.7U L=0.12U M=1
ends INVX4TF
// End of subcircuit definition.

I1 (mida OUTb) INVX4TF
I0 (INa mida) INVX4TF
V0 (INa 0) vsource type=pwl wave=[ 0 0 2n 0 2.1n  1.2 ]

---

OR

--- Hacked Netlist 2 (include file)

simulator lang=spectre
global 0 gnd vdd
include "/remote/eeserv01/software/cadence/Technology/IBM_PDK/cmrf8sf/V1.6.0.3DM/Spectre/models/allModels.scs"
include "ibm13rfvrvt.cdl" // which includes subckt def for INVX4TF

 // NO cmos_sch subckt call here


// Library name: x_asd_testb
// Cell name: std_cell_xx2
// View name: schematic
I1 (mida OUTb) INVX4TF
I0 (INa mida) INVX4TF
V0 (INa 0) vsource type=pwl wave=[ 0 0 2n 0 2.1n  1.2 ]

----

The reason why I can't get Spectre netlist 1 with ADE, is because I don't know how to insert the subckt definition automatically from the large common CDL file into the actual netlist. I've tried BlackBox netlisting and I still can't get this to work.

The reason why I can't get netlist 2 with ADE, is because when I include the large netlist file with all the subcircuits I get an error which states that the subcircuit is being 'redefined'. There are 2 identical subcircuit calls, and I can't figure out a way to remove the INVX4TF cmos_sch subrcircuit calls and keep the instances (I0 and I1) as well. The following is the netlist I normally get from the Virtuoso ADE environment:

------

simulator lang=spectre
global 0 gnd vdd
include "/remote/eeserv01/software/cadence/Technology/IBM_PDK/cmrf8sf/V1.6.0.3DM/Spectre/models/allModels.scs"

include "ibm13rfvrvt.cdl" // which includes subckt def for INVX4TF

 
// Library name: ARM_ibm13rf_reg
// Cell name: INVX4TF
// View name: cmos_sch
subcircuit INVX4TF A Y
M0 vdd a y vdd pfet W=2.34U L=0.12U M=1
M1 y a gnd gnd nfet W=1.7U L=0.12U M=1
ends INVX4TF
// End of subcircuit definition.

-------

I've spent a few days on this problem, but to no avail. I've tried using BlackBox properties, modifiying my .simrc file. Also, I tried creating a new au_cdl view and also tried modifying 'user properties' of the symbol and cmos_sch views. I've also exhausted all documentation and also the Cadence Sourcelink.

Please help, I don't know what to do next.  

Thanks,

Brad

  •  You might want to contact the foundry or fab service that you are using in this case. If you're a mosis customer they have their own message board, http://tech.groups.yahoo.com/group/MOSIS_Users_Group/. 

     

    canuck said:
    5. NO SCHEMATIC VIEW for the std cells

    From http://www.mosis.com/Technical/Designsupport/artisan-instantiate.html 

      These libraries are front-end kits only. They do not contain layout information, SPICE, or netlists.

     

  • Brad,

    Generally what you'll need to do is:

    1. Create a stopping view for each of the  standard cells. For the spectre netlister, you'd normally call this "spectre", and it can be a copy of the symbol.
    2. Edit the Base CDF for the standard cell. In the "Simulation Information" section for spectre, specify the component name as the name of the subckt, and specify the terminal order in the same order they appear in your include file (note the names of the terminals must be the terminal names that are on the symbol, but they must appear in the equivalent order that they do in the SPICE description; SPICE and spectre pass by order).

    Then when you netlist in ADE, providing spectre is in the stop list, and is in the view list before cmos_sch, it will stop when it gets to the spectre view and just write out an instance, using the order from the CDF. The definition of the subckt would then only come from your included file.

    Best Regards,

    Andrew.

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