I am new to cadence environment. I want to import some behavioral VHDL files to cadence and make cell library with it. I DO NOT want to synthesize the design and make layout. How do I go about it ? When I try to import behavioral VHDL files using VHDL In toolbox, it is not getting imported? Does VHDL toolbox import only for structural files?
I think I should elaborate the problem a bit.
I am using Custom IC Design Tools, Virtuoso Front to Back Design Environment IC188.8.131.520.14.
I use Import form in the VHDL toolbox to import .vhd file into virtuoso. As all my files are behavioral, I wanted to know can this VHDL import form import behavioral VHDL files. There is option in the import form "import structural VHDL files as" with options Schematic, netlist and vhdl, what am I supposed to select when the files are behavioral ?
You would need to pick "vhdl". If the code is to be imported as vhdl (rather than as a connectivity database ("netlist") or a full schematic ("schematic")), then you'd pick vhdl. If the code is behavioural it will get imported as vhdl no matter what you pick, because you can't create a schematic from behavioural code.