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ASSURA 3.1.6 error message

yoyega

Hi,

I am working with IC.5.1.4 (Cadence version 07/08) together with austriamicrosystems HitKitV3.70. I am trying to run DRC with ASSURA 3.1.6 on my layout but I get the following error message:

Reading the design data...
*WARNING* Inconsistent DBUPerUU in the design
*WARNING* 160 is not the same as 1000
*WARNING* Cell:  PRIMLIB pcapacitor symbol
Failed to build VDB.
*****  dfIIToVdb terminated abnormally  *****
*WARNING* dfIIToVdb exit with bad status.
*****  aveng terminated abnormally  *****
*WARNING* /ic_tools/v0708/cds/ASSURA.3.1.6/tools/assura/bin/aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated

 I am using austriamicrosystems setup files with design rules. I have been trying to find why are these errors appearing but still have no clue. Can anyone give me any tips?

 

Thanks and regards,

Pedro

  • My guess is that you're trying to run DRC on an inappropriate view. It's complaining about a pcapacitor symbol, which should NOT be in a layout. Symbols often have this DBUperUU.

    Perhaps you accidentally tried to run the DRC on an extracted view? That could well have instances of pcapacitor to represent the extracted parasitics, and I can imagine this would trigger this kind of error.

    Regards,

    Andrew

  •  Hi,

    thank you very much for your answer Andrew. What you say makes sense, but I am sure that I am running the DRC on the layout view. In fact my design has only 2 views: schematic and layout. I don't have an extracted view yet.

     Any other clues/ideas?

    Thanks,

    Pedro

  • Can you try using the "Tree" command (under Design->Hierarchy, I think) to check if you've accidentally managed to get any pcapacitor cells in the layout somehow.

    Also check in the DRC form that you've got the correct lib/cell/view filled in.

    Regards,

    Andrew

  • Hi Andrew, thanks for the clue, it looks like you were right. I have 2 pcapacitor symbols on my layout view! Well, I don't know how did they get there, but I definitely do not see these pcapacitors on the Virtuoso Layout Editing window. Do you know how can I do to see them?

    I checked the DRC form and I have the correct values for lib/cell/view fields.

    Thanks,

    Pedro

     

     

                                              Design Hierarchy
    ****************************************************************************************************
    Library     : tesis_definitivos
    Cell        : phc_lyt
    View        : layout
    Option      : Top to bottom
    Stop Level  : 32
    ****************************************************************************************************

    TECH_C35B4 VIA2_C symbolic (4)
    TECH_C35B4 PD_C symbolic (3)
    TECH_C35B4 VIA1_C symbolic (53)
    TECH_C35B4 ND_C symbolic (3)
    PRIMLIB cpoly layout (2)
    PRIMLIB pcapacitor symbol (2)

    1. Use Edit->Search
    2. Set the search for to be "inst" in "current cellview" and hit the "Add criteria" button.
    3. Set the additional  criteria to be "cellName" == "pcapacitor"
    4. Hit Apply on the form. It should find any pcapacitor instances
    5. Hit the "Select All" (make sure nothing else was selected first)
    6. Use Edit->Delete and the pcapacitors should now be deleted

    After doing these steps, you should have rid yourself of these pcapacitor instances.

    Best Regards,

    Andrew.

  •  Thank you very much Andrew! It worked! I have ASSURA running now!

  •  You are awesome Andrew. Thanks. That problem was buggin me since yesterday. I made a new account on Cadence just to say thank you to you. :)

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