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ASSURA 3.1.6 - errors on input/output pins

yoyega

Hi,
I am using ASSURA for the first time, and I am having some problems, let me explain. I am designing a pixel matrix, I have done the layout for one single pixel, and I am trying to run DRC with ASSURA on this single pixel layout. For the pixel input/output nets I have defined serveral pins using the Create->Pin->shape pin options of Cadence Virtuoso Layout tool. The problem is that assura doesn't seems to recognize these pins. For example, I have defined a vdd! pin connected to the NTUB layer, but ASSURA keeps giving me a warning of HOT NTUB. For the pins defined at the gates of the transistors asssura gives a warning saying 'floating gate not connected...'.

Do you know how should I do to perform a DRC with ASSURA on my pixel layout without receiving these errors/warnings? Is there a way to do it?

Thanks and regards,
Pedro

Parents

  • Pedro,

    This question is very specific to the DRC deck you're using - so you might want to give an indication of which process and rule deck version you're using, so there may be somebody out there with familiarity of that rule set who can give you a response.

    It's unlikely to be anything generic in Assura - it's specific to how those DRC rules have been coded.

    Regards,

    Andrew.

Reply

  • Pedro,

    This question is very specific to the DRC deck you're using - so you might want to give an indication of which process and rule deck version you're using, so there may be somebody out there with familiarity of that rule set who can give you a response.

    It's unlikely to be anything generic in Assura - it's specific to how those DRC rules have been coded.

    Regards,

    Andrew.

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